From: Lu Baolu <baolu.lu@linux.intel.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
iommu@lists.linux-foundation.org,
LKML <linux-kernel@vger.kernel.org>,
Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>
Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>
Subject: Re: [PATCH v8 06/10] iommu/vt-d: Cache virtual command capability register
Date: Wed, 18 Dec 2019 11:25:27 +0800 [thread overview]
Message-ID: <0f704b87-aad7-c864-91ac-423a05287f21@linux.intel.com> (raw)
In-Reply-To: <1576524252-79116-7-git-send-email-jacob.jun.pan@linux.intel.com>
Hi,
On 12/17/19 3:24 AM, Jacob Pan wrote:
> Virtual command registers are used in the guest only, to prevent
> vmexit cost, we cache the capability and store it during initialization.
>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> ---
> drivers/iommu/dmar.c | 1 +
> include/linux/intel-iommu.h | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
> index f2f5d75da94a..3f98dd9ad004 100644
> --- a/drivers/iommu/dmar.c
> +++ b/drivers/iommu/dmar.c
> @@ -953,6 +953,7 @@ static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
> warn_invalid_dmar(phys_addr, " returns all ones");
> goto unmap;
> }
> + iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
>
> /* the registers might be more than one page */
> map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
> index ee26989df008..4d25141ec3df 100644
> --- a/include/linux/intel-iommu.h
> +++ b/include/linux/intel-iommu.h
> @@ -189,6 +189,9 @@
> #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
> #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
>
> +/* Virtual command interface capabilities */
> +#define vccap_pasid(v) ((v & DMA_VCS_PAS)) /* PASID allocation */
Has DMA_VCS_PAS ever been defined?
Best regards,
baolu
> +
> /* IOTLB_REG */
> #define DMA_TLB_FLUSH_GRANU_OFFSET 60
> #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
> @@ -531,6 +534,7 @@ struct intel_iommu {
> u64 reg_size; /* size of hw register set */
> u64 cap;
> u64 ecap;
> + u64 vccap;
> u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
> raw_spinlock_t register_lock; /* protect register handling */
> int seq_id; /* sequence id of the iommu */
>
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next prev parent reply other threads:[~2019-12-18 3:26 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-16 19:24 [PATCH v8 00/10] Nested Shared Virtual Address (SVA) VT-d support Jacob Pan
2019-12-16 19:24 ` [PATCH v8 01/10] iommu/vt-d: Move domain helper to header Jacob Pan
2019-12-16 19:24 ` [PATCH v8 02/10] iommu/vt-d: Add nested translation helper function Jacob Pan
2019-12-18 2:01 ` Lu Baolu
2020-01-09 17:51 ` Jacob Pan
2019-12-18 2:41 ` Lu Baolu
2020-01-09 18:39 ` Jacob Pan
2020-01-10 1:15 ` Lu Baolu
2020-01-10 18:25 ` Jacob Pan
2019-12-16 19:24 ` [PATCH v8 03/10] iommu/vt-d: Add bind guest PASID support Jacob Pan
2019-12-18 3:14 ` Lu Baolu
2020-01-09 21:45 ` Jacob Pan
2019-12-16 19:24 ` [PATCH v8 04/10] iommu/vt-d: Support flushing more translation cache types Jacob Pan
2019-12-19 2:46 ` Lu Baolu
2020-01-09 21:50 ` Jacob Pan
2020-01-10 1:17 ` Lu Baolu
2019-12-16 19:24 ` [PATCH v8 05/10] iommu/vt-d: Add svm/sva invalidate function Jacob Pan
2019-12-16 19:24 ` [PATCH v8 06/10] iommu/vt-d: Cache virtual command capability register Jacob Pan
2019-12-18 3:25 ` Lu Baolu [this message]
2020-01-09 21:59 ` Jacob Pan
2019-12-16 19:24 ` [PATCH v8 07/10] iommu/vt-d: Enlightened PASID allocation Jacob Pan
2019-12-16 19:24 ` [PATCH v8 08/10] iommu/vt-d: Add custom allocator for IOASID Jacob Pan
2019-12-18 4:10 ` Lu Baolu
2020-01-09 22:06 ` Jacob Pan
2020-01-10 1:19 ` Lu Baolu
2019-12-16 19:24 ` [PATCH v8 09/10] iommu/ioasid: Add notifier for status change Jacob Pan
2019-12-16 19:24 ` [PATCH v8 10/10] iommu/vt-d: Handle IOASID notifications Jacob Pan
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