[GIT PULL] VT-d hardware workarounds for 4.1

[David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>]

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Linus, please pull, again, from
	git://git.infradead.org/intel-iommu.git

This contains a workaround for hardware issues which I *thought* were
never going to be seen on production hardware. I'm glad I checked that
before the 4.1 release...

Firstly, PASID support is so broken on existing chips that we're just
going to declare the old capability bit 28 as 'reserved' and change the
VT-d spec to move PASID support to another bit. So any existing
hardware doesn't support SVM; it only sets that (now) meaningless bit
28.

That patch *wasn't* imperative for 4.1 because we don't have PASID
support yet. But *even* the extended context tables are broken — if you
just enable the wider tables and use none of the new bits in them,
which is precisely what 4.1 does, you find that translations don't
work. It's this problem which I thought was caught in time to be fixed
before production, but wasn't.

To avoid triggering this issue, we now *only* enable the extended
context tables on hardware which also advertises "we have PASID support
and we actually tested it this time" with the new PASID feature bit.

In addition, I've added an 'intel_iommu=ecs_off' command line parameter
to allow us to disable it manually if we need to.

David Woodhouse (2):
      iommu/vt-d: Change PASID support to bit 40 of Extended Capability Register
      iommu/vt-d: Only enable extended context tables if PASID is supported

 Documentation/kernel-parameters.txt |  6 ++++++
 drivers/iommu/intel-iommu.c         | 18 +++++++++++++++---
 include/linux/intel-iommu.h         |  3 ++-
 3 files changed, 23 insertions(+), 4 deletions(-)

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org                              Intel Corporation

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