From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Woodhouse Subject: [PATCH 4/7] iommu/vt-d: Generalise DMAR MSI setup to allow for page request events Date: Fri, 09 Oct 2015 00:53:14 +0100 Message-ID: <1444348394.92154.32.camel@infradead.org> References: <1444348223.92154.22.camel@infradead.org> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1561301678==" Return-path: In-Reply-To: <1444348223.92154.22.camel@infradead.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: iommu@lists.linux-foundation.org, intel-gfx@lists.freedesktop.org, jesse.barnes@intel.com List-Id: iommu@lists.linux-foundation.org --===============1561301678== Content-Type: multipart/signed; micalg="sha-1"; protocol="application/x-pkcs7-signature"; boundary="=-G8m2w0DBc3PZDpksdHOz" --=-G8m2w0DBc3PZDpksdHOz Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Signed-off-by: David Woodhouse --- drivers/iommu/dmar.c | 42 +++++++++++++++++++++++++++++++----------= - include/linux/intel-iommu.h | 10 +++++++++- 2 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index 8757f8d..80e3c17 100644 --- a/drivers/iommu/dmar.c +++ b/drivers/iommu/dmar.c @@ -1086,6 +1086,11 @@ static void free_iommu(struct intel_iommu *iommu) iommu_device_destroy(iommu->iommu_dev); =20 if (iommu->irq) { + if (iommu->pr_irq) { + free_irq(iommu->pr_irq, iommu); + dmar_free_hwirq(iommu->pr_irq); + iommu->pr_irq =3D 0; + } free_irq(iommu->irq, iommu); dmar_free_hwirq(iommu->irq); iommu->irq =3D 0; @@ -1493,53 +1498,68 @@ static const char *dmar_get_fault_reason(u8 fault_r= eason, int *fault_type) } } =20 + +static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) +{ + if (iommu->irq =3D=3D irq) + return DMAR_FECTL_REG; + else if (iommu->pr_irq =3D=3D irq) + return DMAR_PECTL_REG; + else + BUG(); +} + void dmar_msi_unmask(struct irq_data *data) { struct intel_iommu *iommu =3D irq_data_get_irq_handler_data(data); + int reg =3D dmar_msi_reg(iommu, data->irq); unsigned long flag; =20 /* unmask it */ raw_spin_lock_irqsave(&iommu->register_lock, flag); - writel(0, iommu->reg + DMAR_FECTL_REG); + writel(0, iommu->reg + reg); /* Read a reg to force flush the post write */ - readl(iommu->reg + DMAR_FECTL_REG); + readl(iommu->reg + reg); raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } =20 void dmar_msi_mask(struct irq_data *data) { - unsigned long flag; struct intel_iommu *iommu =3D irq_data_get_irq_handler_data(data); + int reg =3D dmar_msi_reg(iommu, data->irq); + unsigned long flag; =20 /* mask it */ raw_spin_lock_irqsave(&iommu->register_lock, flag); - writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG); + writel(DMA_FECTL_IM, iommu->reg + reg); /* Read a reg to force flush the post write */ - readl(iommu->reg + DMAR_FECTL_REG); + readl(iommu->reg + reg); raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } =20 void dmar_msi_write(int irq, struct msi_msg *msg) { struct intel_iommu *iommu =3D irq_get_handler_data(irq); + int reg =3D dmar_msi_reg(iommu, irq); unsigned long flag; =20 raw_spin_lock_irqsave(&iommu->register_lock, flag); - writel(msg->data, iommu->reg + DMAR_FEDATA_REG); - writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG); - writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG); + writel(msg->data, iommu->reg + reg + 4); + writel(msg->address_lo, iommu->reg + reg + 8); + writel(msg->address_hi, iommu->reg + reg + 12); raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } =20 void dmar_msi_read(int irq, struct msi_msg *msg) { struct intel_iommu *iommu =3D irq_get_handler_data(irq); + int reg =3D dmar_msi_reg(iommu, irq); unsigned long flag; =20 raw_spin_lock_irqsave(&iommu->register_lock, flag); - msg->data =3D readl(iommu->reg + DMAR_FEDATA_REG); - msg->address_lo =3D readl(iommu->reg + DMAR_FEADDR_REG); - msg->address_hi =3D readl(iommu->reg + DMAR_FEUADDR_REG); + msg->data =3D readl(iommu->reg + reg + 4); + msg->address_lo =3D readl(iommu->reg + reg + 8); + msg->address_hi =3D readl(iommu->reg + reg + 12); raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } =20 diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index b0df572..564a61b 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -59,6 +59,14 @@ #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register *= / +#define DMAR_PQH_REG 0xc0 /* Page request queue head register */ +#define DMAR_PQT_REG 0xc8 /* Page request queue tail register */ +#define DMAR_PQA_REG 0xd0 /* Page request queue address register */ +#define DMAR_PRS_REG 0xdc /* Page request status register */ +#define DMAR_PECTL_REG 0xe0 /* Page request event control register */ +#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register= */ +#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register= */ +#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register= */ =20 #define OFFSET_STRIDE (9) /* @@ -374,7 +382,7 @@ struct intel_iommu { int seq_id; /* sequence id of the iommu */ int agaw; /* agaw of this iommu */ int msagaw; /* max sagaw of this iommu */ - unsigned int irq; + unsigned int irq, pr_irq; u16 segment; /* PCI segment# */ unsigned char name[13]; /* Device Name */ =20 --=20 2.4.3 --=20 David Woodhouse Open Source Technology Centre David.Woodhouse@intel.com Intel Corporation --=-G8m2w0DBc3PZDpksdHOz Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExCzAJBgUrDgMCGgUAMIAGCSqGSIb3DQEHAQAAoIISjjCCBicw ggUPoAMCAQICAw3vNzANBgkqhkiG9w0BAQUFADCBjDELMAkGA1UEBhMCSUwxFjAUBgNVBAoTDVN0 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