From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulpanit Subject: [PATCH V5 01/10] perf/amd/iommu: Misc fix up perf_iommu_read Date: Tue, 23 Feb 2016 08:12:35 -0600 Message-ID: <1456236764-1569-2-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1456236764-1569-1-git-send-email-Suravee.Suthikulpanit@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1456236764-1569-1-git-send-email-Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, bp-Gina5bIWoIWzQB+pC5nmwQ@public.gmane.org, peterz-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, mingo-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, acme-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, andihartmann-KuiJ5kEpwI6ELgA04lAiVw@public.gmane.org, labbott-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org List-Id: iommu@lists.linux-foundation.org This patch contains the follow minor fixup: * Fixed overflow handling since u64 delta would lose the MSB sign bit. * Remove unnecessary local64_set(). * Coding style and make use of GENMASK_ULL macro. Cc: Peter Zijlstra Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 629bc70..9da0d16 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -314,9 +314,8 @@ static void perf_iommu_start(struct perf_event *event, int flags) static void perf_iommu_read(struct perf_event *event) { - u64 count = 0ULL; - u64 prev_raw_count = 0ULL; - u64 delta = 0ULL; + u64 cnt, prev; + s64 delta; struct hw_perf_event *hwc = &event->hw; pr_debug("perf: amd_iommu:perf_iommu_read\n"); @@ -325,18 +324,20 @@ static void perf_iommu_read(struct perf_event *event) IOMMU_PC_COUNTER_REG, &count, false); /* IOMMU pc counter register is only 48 bits */ - count &= 0xFFFFFFFFFFFFULL; + cnt &= GENMASK_ULL(48, 0); - prev_raw_count = local64_read(&hwc->prev_count); - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - count) != prev_raw_count) - return; + prev = local64_read(&hwc->prev_count); - /* Handling 48-bit counter overflowing */ - delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT); + /* + * Since we do not enable counter overflow interrupts, + * we do not have to worry about prev_count changing on us. + */ + local64_set(&hwc->prev_count, cnt); + + /* Handle 48-bit counter overflow */ + delta = (cnt << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); delta >>= COUNTER_SHIFT; local64_add(delta, &event->count); - } static void perf_iommu_stop(struct perf_event *event, int flags) -- 1.9.1