From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulpanit Subject: [PATCH V5 06/10] perf/amd/iommu: Clean up perf_iommu_enable_event Date: Tue, 23 Feb 2016 08:12:40 -0600 Message-ID: <1456236764-1569-7-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1456236764-1569-1-git-send-email-Suravee.Suthikulpanit@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1456236764-1569-1-git-send-email-Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, bp-Gina5bIWoIWzQB+pC5nmwQ@public.gmane.org, peterz-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, mingo-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, acme-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, andihartmann-KuiJ5kEpwI6ELgA04lAiVw@public.gmane.org, labbott-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org List-Id: iommu@lists.linux-foundation.org This patch cleans up: * Various bitwise operations in perf_iommu_enable_event * Make use macros BIT(x) This should not affect logic and functionality. Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index ee7b4d3..1a678b9 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -253,21 +253,21 @@ static void perf_iommu_enable_event(struct perf_event *ev) amd_iommu_pc_set_reg(0, devid, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, ®); - reg = 0ULL | devid | (_GET_DEVID_MASK(ev) << 32); + reg = devid | (_GET_DEVID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_set_reg(0, devid, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, ®); - reg = 0ULL | _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32); + reg = _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_set_reg(0, devid, bank, cntr, IOMMU_PC_PASID_MATCH_REG, ®); - reg = 0ULL | _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32); + reg = _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_set_reg(0, devid, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, ®); } -- 1.9.1