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From: Sohil Mehta <sohil.mehta-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>,
	Alex Williamson
	<alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Cc: Ravi V Shankar
	<ravi.v.shankar-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	Fenghua Yu <fenghua.yu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Dave Hansen <dave.hansen-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
	David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
	Gayatri Kammela
	<gayatri.kammela-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	Kirill Shutemov
	<kirill.shutemov-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
	Andy Shevchenko
	<andriy.shevchenko-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Subject: [PATCH 2/4] iommu/vt-d: Add a check for 1GB page support
Date: Wed, 20 Dec 2017 11:59:25 -0800	[thread overview]
Message-ID: <1513799967-22454-3-git-send-email-sohil.mehta@intel.com> (raw)
In-Reply-To: <1513799967-22454-1-git-send-email-sohil.mehta-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>

Add a check to verify IOMMU 1GB page support. If the CPU supports 1GB
pages but the IOMMU does not support it then disable SVM by not
allocating PASID tables.

Signed-off-by: Sohil Mehta <sohil.mehta-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
 drivers/iommu/intel-svm.c   | 4 ++++
 include/linux/intel-iommu.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index ed1cf7c..fcab440 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -41,6 +41,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
 	struct page *pages;
 	int order;
 
+	if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
+			!cap_fl1gp_support(iommu->cap))
+		return -EINVAL;
+
 	/* Start at 2 because it's defined as 2^(1+PSS) */
 	iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
 
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index f3274d9..a56bab1 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -84,6 +84,7 @@
  * Decoding Capability Register
  */
 #define cap_pi_support(c)	(((c) >> 59) & 1)
+#define cap_fl1gp_support(c)	(((c) >> 56) & 1)
 #define cap_read_drain(c)	(((c) >> 55) & 1)
 #define cap_write_drain(c)	(((c) >> 54) & 1)
 #define cap_max_amask_val(c)	(((c) >> 48) & 0x3f)
-- 
2.7.4

  parent reply	other threads:[~2017-12-20 19:59 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-20 19:59 [PATCH 0/4] Add support for Intel IOMMU 5-level paging Sohil Mehta
     [not found] ` <1513799967-22454-1-git-send-email-sohil.mehta-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-12-20 19:59   ` [PATCH 1/4] iommu/vt-d: Enable upto 57 bits of domain address width Sohil Mehta
2017-12-20 19:59   ` Sohil Mehta [this message]
2017-12-20 19:59   ` [PATCH 3/4] iommu/vt-d: Add a check for 5-level paging support Sohil Mehta
2017-12-20 19:59   ` [PATCH 4/4] iommu/vt-d: Enable 5-level paging mode in the PASID entry Sohil Mehta
2018-01-17 14:03   ` [PATCH 0/4] Add support for Intel IOMMU 5-level paging Joerg Roedel

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