From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulpanit Subject: [PATCH 0/3] iommu/amd: Enable x2APIC support Date: Fri, 22 Jun 2018 12:02:04 -0500 Message-ID: <1529686927-7665-1-git-send-email-suravee.suthikulpanit@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: jroedel-l3A5Bk7waGM@public.gmane.org List-Id: iommu@lists.linux-foundation.org This series enable x2APIC support for AMD platform by enabling AMD IOMMU XT mode to allow interrupt remapping with 32-bit destination APIC ID. For full x2APIC support, the following patches are also required (already available in v4.18-rc1) * 6c4f5abaf356 ("x86/CPU: Modify detect_extended_topology() to return result") * 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available") Thanks, Suravee Suravee Suthikulpanit (3): x86: irq_remapping: Move irq remapping mode enum iommu/amd: Add support for higher 64-bit IOMMU Control Register iommu/amd: Add support for IOMMU XT mode arch/x86/include/asm/irq_remapping.h | 5 ++++ drivers/iommu/amd_iommu.c | 21 +++++++++++---- drivers/iommu/amd_iommu_init.c | 51 +++++++++++++++++++++++++----------- drivers/iommu/amd_iommu_types.h | 17 +++++++----- include/linux/dmar.h | 5 ---- 5 files changed, 68 insertions(+), 31 deletions(-) -- 2.7.4