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X-CSE-ConnectionGUID: PdMA9T72SS6JEAOO/TVLbw== X-CSE-MsgGUID: ++Hud8dUTxWRhOrIFwOiWg== X-IronPort-AV: E=McAfee;i="6800,10657,11499"; a="66739965" X-IronPort-AV: E=Sophos;i="6.16,330,1744095600"; d="scan'208";a="66739965" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2025 22:20:03 -0700 X-CSE-ConnectionGUID: 99yeqcaeT+evCr9eoblOiw== X-CSE-MsgGUID: d60c7TEaTVuuurymKyR0sw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,330,1744095600"; d="scan'208";a="158688984" Received: from allen-sbox.sh.intel.com (HELO [10.239.159.30]) ([10.239.159.30]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2025 22:20:01 -0700 Message-ID: <158774a0-824f-42a7-93c9-fb1e0d258cc7@linux.intel.com> Date: Tue, 22 Jul 2025 13:17:59 +0800 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT To: Jason Gunthorpe , David Woodhouse , iommu@lists.linux.dev, Joerg Roedel , Robin Murphy , Will Deacon Cc: Kevin Tian , patches@lists.linux.dev, Tina Zhang , Wei Wang References: <7-v1-bdb01ffac49c+be-iommu_pt_vtd_jgg@nvidia.com> Content-Language: en-US From: Baolu Lu In-Reply-To: <7-v1-bdb01ffac49c+be-iommu_pt_vtd_jgg@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/17/25 03:57, Jason Gunthorpe wrote: > VT-D requires PT_FEAT_DMA_INCOHERENT for the x86 page table as well, > implement the required SW bits and enable the feature. > > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/generic_pt/fmt/iommu_x86_64.c | 2 +- > drivers/iommu/generic_pt/fmt/x86_64.h | 27 +++++++++++++++++++++ > 2 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/generic_pt/fmt/iommu_x86_64.c b/drivers/iommu/generic_pt/fmt/iommu_x86_64.c > index 5c5960d871a32f..5472660c2d7156 100644 > --- a/drivers/iommu/generic_pt/fmt/iommu_x86_64.c > +++ b/drivers/iommu/generic_pt/fmt/iommu_x86_64.c > @@ -6,6 +6,6 @@ > #define PT_SUPPORTED_FEATURES \ > (BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | \ > BIT(PT_FEAT_FLUSH_RANGE_NO_GAPS) | \ > - BIT(PT_FEAT_X86_64_AMD_ENCRYPT_TABLES)) > + BIT(PT_FEAT_X86_64_AMD_ENCRYPT_TABLES) | BIT(PT_FEAT_DMA_INCOHERENT)) > > #include "iommu_template.h" > diff --git a/drivers/iommu/generic_pt/fmt/x86_64.h b/drivers/iommu/generic_pt/fmt/x86_64.h > index 60f8bd6b164b54..1b691f7cbf82d8 100644 > --- a/drivers/iommu/generic_pt/fmt/x86_64.h > +++ b/drivers/iommu/generic_pt/fmt/x86_64.h > @@ -160,6 +160,33 @@ static inline void x86_64_pt_attr_from_entry(const struct pt_state *pts, > } > #define pt_attr_from_entry x86_64_pt_attr_from_entry > > +static inline unsigned int x86_64_pt_max_sw_bit(struct pt_common *common) > +{ > + return 12; > +} > +#define pt_max_sw_bit x86_64_pt_max_sw_bit > + > +static inline u64 x86_64_pt_sw_bit(unsigned int bitnr) > +{ > + /* Bits marked Ignored/AVL in the specification */ > + switch (bitnr) { > + case 0: > + return BIT(9); > + case 1: > + return BIT(11); > + case 2 ... 12: > + return BIT_ULL((bitnr - 2) + 52); Just out of curiosity, why bit 63 can't be used as the sw bit? > + /* Remaing bits 9-8,6,4,3 are only available in some entries */ > + default: > + if (__builtin_constant_p(bitnr)) > + BUILD_BUG(); > + else > + PT_WARN_ON(true); > + return 0; > + } > +} > +#define pt_sw_bit x86_64_pt_sw_bit > + > /* --- iommu */ > #include > #include Looks good to me. Reviewed-by: Lu Baolu Thanks, baolu