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X-UUID: 5141fc99c02e4a1f8b70cbc146099df1-20201026 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 375836218; Mon, 26 Oct 2020 15:45:43 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Oct 2020 15:45:35 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Oct 2020 15:45:34 +0800 Message-ID: <1603698334.26323.88.camel@mhfsdcap03> Subject: Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek From: Yong Wu To: Will Deacon Date: Mon, 26 Oct 2020 15:45:34 +0800 In-Reply-To: <20201023112148.GB20933@willie-the-truck> References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-12-yong.wu@mediatek.com> <20201023112148.GB20933@willie-the-truck> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 7D5007B554F3125CBCD9B8D492C92003C020E35494172D92BAFD6D3255A98BE82000:8 X-MTK: N Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, kernel-team@android.com, Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Fri, 2020-10-23 at 12:21 +0100, Will Deacon wrote: > On Wed, Sep 30, 2020 at 03:06:34PM +0800, Yong Wu wrote: > > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable > > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach > > 34bit. > > > > Signed-off-by: Yong Wu > > --- > > drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++--- > > drivers/iommu/mtk_iommu.c | 2 +- > > 2 files changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > > index 8362fdf76657..306bae2755ed 100644 > > --- a/drivers/iommu/io-pgtable-arm-v7s.c > > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > > @@ -50,10 +50,17 @@ > > */ > > #define ARM_V7S_ADDR_BITS 32 > > If we rename this to _ARM_V7S_ADDR_BITS can we then have ARM_V7S_ADDR_BITS > take a cfg parameter and move the arm_v7s_is_mtk_enabled() check in there? > Same for _ARM_V7S_LVL_BITS. > > That would avoid scattering arm_v7s_is_mtk_enabled() into all the users. I added "cfg" for _ARM_V7S_LVL_BITS in Robin's mail. is that ok? Regarding ARM_V7S_ADDR_BITS, I'd like to keep it as is(Don't add cfg), this macro only is used in ARM_V7S_LVL_SHIFT and checking the value of ias/oas. a) ARM_V7S_LVL_SHIFT always expect ARM_V7S_ADDR_BITS is 32. b) our ias/oas is different(ias is 34 while oas is 35). If we define a new macro, we need two about this, like: #define ARM_V7S_IADDR_BITS(cfg) (!arm_v7s_is_mtk_enabled(cfg) ? 32 : 34) #define ARM_V7S_OADDR_BITS(cfg) (!arm_v7s_is_mtk_enabled(cfg) ? 32 : 35) and the two will only are used in the checking of ias/oas. thus it looks unnecessary? > > Will _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu