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X-UUID: 75617dd10cbf41aa8a8aa93cbb70916a-20201229 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 794393449; Tue, 29 Dec 2020 19:06:28 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Dec 2020 19:06:18 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 29 Dec 2020 19:06:18 +0800 Message-ID: <1609239977.26323.292.camel@mhfsdcap03> Subject: Re: [PATCH v5 18/27] iommu/mediatek: Add power-domain operation From: Yong Wu To: Tomasz Figa Date: Tue, 29 Dec 2020 19:06:17 +0800 In-Reply-To: References: <20201209080102.26626-1-yong.wu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: D6856EB35728775B524D669116D09ECF5C09C39014423CFC3B03E7EB5EA35C712000:8 X-MTK: N Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, Tomasz Figa , Will Deacon , linux-kernel@vger.kernel.org, Evan Green , chao.hao@mediatek.com, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Matthias Brugger , anan.sun@mediatek.com, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, 2020-12-23 at 17:36 +0900, Tomasz Figa wrote: > On Wed, Dec 09, 2020 at 04:00:53PM +0800, Yong Wu wrote: > > In the previous SoC, the M4U HW is in the EMI power domain which is > > always on. the latest M4U is in the display power domain which may be > > turned on/off, thus we have to add pm_runtime interface for it. > > > > When the engine work, the engine always enable the power and clocks for > > smi-larb/smi-common, then the M4U's power will always be powered on > > automatically via the device link with smi-common. > > > > Note: we don't enable the M4U power in iommu_map/unmap for tlb flush. > > If its power already is on, of course it is ok. if the power is off, > > the main tlb will be reset while M4U power on, thus the tlb flush while > > m4u power off is unnecessary, just skip it. > > > > There will be one case that pm runctime status is not expected when tlb > > flush. After boot, the display may call dma_alloc_attrs before it call > > pm_runtime_get(disp-dev), then the m4u's pm status is not active inside > > the dma_alloc_attrs. Since it only happens after boot, the tlb is clean > > at that time, I also think this is ok. > > > > Signed-off-by: Yong Wu > > --- > > drivers/iommu/mtk_iommu.c | 41 +++++++++++++++++++++++++++++++++------ > > 1 file changed, 35 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 6fe3ee2b2bf5..0e9c03cbab32 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -184,6 +184,8 @@ static void mtk_iommu_tlb_flush_all(void *cookie) > > struct mtk_iommu_data *data = cookie; > > > > for_each_m4u(data) { > > + if (!pm_runtime_active(data->dev)) > > + continue; > > Is it guaranteed that the status is active in the check above, but then > the process is preempted and it goes down here? > > Shouldn't we do something like below? > > ret = pm_runtime_get_if_active(); > if (!ret) > continue; > if (ret < 0) > // handle error > > // Flush > > pm_runtime_put(); Make sense. Thanks. There is a comment in arm_smmu.c "avoid touching dev->power.lock in fastpaths". To avoid this here too(we have many SoC don't have power-domain). then the code will be like: bool has_pm = !!data->dev->pm_domain; if (has_pm) { if (pm_runtime_get_if_in_use(data->dev) <= 0) continue; } xxxx if (has_pm) pm_runtime_put(data->dev); > > Similar comment to the other places being changed by this patch. > > > writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, > > data->base + data->plat_data->inv_sel_reg); > > writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); > > @@ -200,6 +202,10 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, > > u32 tmp; > > > > for_each_m4u(data) { > > + /* skip tlb flush when pm is not active. */ > > + if (!pm_runtime_active(data->dev)) > > + continue; > > + > > spin_lock_irqsave(&data->tlb_lock, flags); > > writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, > > data->base + data->plat_data->inv_sel_reg); [snip] _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu