From: Robin Murphy <robin.murphy@arm.com>
To: Will Deacon <will@kernel.org>
Cc: mark.rutland@arm.com, prime.zeng@huawei.com,
alexander.shishkin@linux.intel.com, linux-pci@vger.kernel.org,
linuxarm@huawei.com, Yicong Yang <yangyicong@hisilicon.com>,
daniel.thompson@linaro.org, peterz@infradead.org,
mingo@redhat.com, helgaas@kernel.org, liuqi115@huawei.com,
mike.leach@linaro.org, suzuki.poulose@arm.com,
coresight@lists.linaro.org, acme@kernel.org,
zhangshaokun@hisilicon.com, linux-arm-kernel@lists.infradead.org,
mathieu.poirier@linaro.org, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
iommu@lists.linux-foundation.org, leo.yan@linaro.org,
Yicong Yang <yangyicong@huawei.com>
Subject: Re: [PATCH v3 8/8] iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity
Date: Tue, 15 Feb 2022 14:29:27 +0000 [thread overview]
Message-ID: <161e5005-ea12-fde4-0e31-ec871d2fe591@arm.com> (raw)
In-Reply-To: <20220215134232.GA7592@willie-the-truck>
On 2022-02-15 13:42, Will Deacon wrote:
> On Tue, Feb 15, 2022 at 01:30:26PM +0000, Robin Murphy wrote:
>> On 2022-02-15 13:00, Will Deacon wrote:
>>> On Mon, Feb 14, 2022 at 08:55:20PM +0800, Yicong Yang wrote:
>>>> On 2022/1/24 21:11, Yicong Yang wrote:
>>>>> The DMA of HiSilicon PTT device can only work with identical
>>>>> mapping. So add a quirk for the device to force the domain
>>>>> passthrough.
>>>>>
>>>>> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
>>>>> ---
>>>>> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++++
>>>>> 1 file changed, 16 insertions(+)
>>>>>
>>>>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>>>>> index 6dc6d8b6b368..6f67a2b1dd27 100644
>>>>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>>>>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>>>>> @@ -2838,6 +2838,21 @@ static int arm_smmu_dev_disable_feature(struct device *dev,
>>>>> }
>>>>> }
>>>>> +#define IS_HISI_PTT_DEVICE(pdev) ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI && \
>>>>> + (pdev)->device == 0xa12e)
>>>>> +
>>>>> +static int arm_smmu_def_domain_type(struct device *dev)
>>>>> +{
>>>>> + if (dev_is_pci(dev)) {
>>>>> + struct pci_dev *pdev = to_pci_dev(dev);
>>>>> +
>>>>> + if (IS_HISI_PTT_DEVICE(pdev))
>>>>> + return IOMMU_DOMAIN_IDENTITY;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> static struct iommu_ops arm_smmu_ops = {
>>>>> .capable = arm_smmu_capable,
>>>>> .domain_alloc = arm_smmu_domain_alloc,
>>>>> @@ -2863,6 +2878,7 @@ static struct iommu_ops arm_smmu_ops = {
>>>>> .sva_unbind = arm_smmu_sva_unbind,
>>>>> .sva_get_pasid = arm_smmu_sva_get_pasid,
>>>>> .page_response = arm_smmu_page_response,
>>>>> + .def_domain_type = arm_smmu_def_domain_type,
>>>>> .pgsize_bitmap = -1UL, /* Restricted during device attach */
>>>>> .owner = THIS_MODULE,
>>>>> };
>>>>>
>>>>
>>>> Is this quirk ok with the SMMU v3 driver? Just want to confirm that I'm on the
>>>> right way to dealing with the issue of our device.
>>>
>>> I don't think the quirk should be in the SMMUv3 driver. Assumedly, you would
>>> have the exact same problem if you stuck the PTT device behind a different
>>> type of IOMMU, and so the quirk should be handled by a higher level of the
>>> stack.
>>
>> Conceptually, yes, but I'm inclined to be pragmatic here. Default domain
>> quirks could only move out as far as the other end of the call from
>> iommu_get_def_domain_type() - it's not like we could rely on some flag in a
>> driver which may not even be loaded yet, let alone matched to the device.
>> And even then there's an equal and opposite argument for why the core code
>> should have to maintain a list of platform-specific quirks rather than code
>> specific to the relevant platforms. The fact is that a HiSilicon RCiEP is
>> not going to end up behind anything other than a HiSilicon IOMMU, and if
>> those ever stop being SMMUv3 *and* such a quirk still exists we can worry
>> about it then.
>
> Perhaps, but you know that by adding this hook it's only a matter of time
> before we get random compatible string matches in there, so I'd rather keep
> the flood gates closed as long as we can.
>
> Given that this is a PCI device, why can't we have a PCI quirk for devices
> which require an identity mapping and then handle that in the IOMMU core?
Oh, don't think I *like* having quirks in the driver, it just seems like
the least-worst choice from a bad bunch. All of the default domain
quirks so far (including this one) exist for integrated devices and/or
dodgy firmware setups such that they are platform-specific, so there is
no technical reason for trying to split *some* of them off into a
generic mechanism when the driver-based platform-specific mechanism
still needs to exist anyway (some of them do depend on driver state as
well).
Feel free to test the waters with a patch punting
qcom_smmu_def_domain_type() to core code, but I think you'll struggle to
find a reason to give in the commit message other than "I don't like it".
>> Ugly as it is, this is the status quo. I don't recall anyone ever arguing
>> that the equivalent quirks for Intel integrated graphics should be made
>> generic ;)
>
> I don't know anything about Intel integrated graphics. Have they solved this
> problem in a better way, or could they equally make use of a generic quirk?
See intel-iommu's device_def_domain_type() implementation. The shape of
it may seem quite familiar...
Robin.
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next prev parent reply other threads:[~2022-02-15 14:29 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 13:11 [PATCH v3 0/8] Add support for HiSilicon PCIe Tune and Trace device Yicong Yang via iommu
2022-01-24 13:11 ` [PATCH v3 1/8] hwtracing: Add trace function " Yicong Yang via iommu
2022-02-07 11:42 ` Jonathan Cameron via iommu
2022-02-08 11:07 ` Yicong Yang via iommu
2022-02-14 12:51 ` Yicong Yang via iommu
2022-02-07 18:11 ` John Garry via iommu
2022-02-08 8:57 ` Yicong Yang via iommu
2022-01-24 13:11 ` [PATCH v3 2/8] hisi_ptt: Register PMU device for PTT trace Yicong Yang via iommu
2022-02-07 11:42 ` Jonathan Cameron via iommu
2022-02-08 7:41 ` Yicong Yang via iommu
2022-01-24 13:11 ` [PATCH v3 3/8] hisi_ptt: Add support for dynamically updating the filter list Yicong Yang via iommu
2022-01-24 13:11 ` [PATCH v3 4/8] hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device Yicong Yang via iommu
2022-02-07 11:49 ` Jonathan Cameron via iommu
2022-02-08 7:08 ` Yicong Yang via iommu
2022-01-24 13:11 ` [PATCH v3 5/8] perf tool: Add support for HiSilicon PCIe Tune and Trace device driver Yicong Yang via iommu
2022-02-07 11:55 ` Jonathan Cameron via iommu
2022-01-24 13:11 ` [PATCH v3 6/8] docs: Add HiSilicon PTT device driver documentation Yicong Yang via iommu
2022-02-07 12:12 ` Jonathan Cameron via iommu
2022-02-08 11:09 ` Yicong Yang via iommu
2022-01-24 13:11 ` [PATCH v3 7/8] MAINTAINERS: Add maintainer for HiSilicon PTT driver Yicong Yang via iommu
2022-01-24 13:11 ` [PATCH v3 8/8] iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity Yicong Yang via iommu
2022-02-08 8:05 ` John Garry via iommu
2022-02-08 11:21 ` Yicong Yang via iommu
2022-02-08 11:56 ` John Garry via iommu
2022-02-08 12:20 ` Yicong Yang via iommu
2022-02-14 12:55 ` Yicong Yang via iommu
2022-02-15 13:00 ` Will Deacon
2022-02-15 13:30 ` Robin Murphy
2022-02-15 13:42 ` Will Deacon
2022-02-15 14:29 ` Robin Murphy [this message]
2022-02-16 9:35 ` Yicong Yang via iommu
2022-02-07 9:40 ` [PATCH v3 0/8] Add support for HiSilicon PCIe Tune and Trace device Yicong Yang via iommu
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