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b=AzDdA2JmY3JXcQjf4KRlTgeOVef8J0NRQ3sCNkds955AhMpRPyKxdWAhlLsv2RR1Soao421TCNDa6m/3HxVde2JN8NhwO/j2H6bjU8xgSbLame2sHJLVCQlfJ90zMzYmDqDsl4y9RRKw383zRBumVdSWM6JEaeqUSsvGykRM+To=; X-UUID: ea3b0ad1d7ae491e9e3dbd38de65456e-20210722 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 715036884; Thu, 22 Jul 2021 14:38:25 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Jul 2021 14:38:24 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Jul 2021 14:38:22 +0800 Message-ID: <1626935902.27875.7.camel@mhfsdcap03> Subject: Re: [PATCH v2 11/11] memory: mtk-smi: mt8195: Add initial setting for smi-larb From: Yong Wu To: Ikjoon Jang Date: Thu, 22 Jul 2021 14:38:22 +0800 In-Reply-To: References: <20210715121209.31024-1-yong.wu@mediatek.com> <20210715121209.31024-12-yong.wu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , srv_heupstream , Krzysztof Kozlowski , Robin Murphy , open list , Krzysztof Kozlowski , iommu@lists.linux-foundation.org, Rob Herring , "moderated list:ARM/Mediatek SoC support" , Matthias Brugger , Will Deacon , "moderated list:ARM/Mediatek SoC support" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu wrote: > > > > To improve the performance, We add some initial setting for smi larbs. > > there are two part: > > 1), Each port has the special ostd(outstanding) value in each larb. > > 2), Two general setting for each larb. > > > > In some SoC, this setting maybe changed dynamically for some special case > > like 4K, and this initial setting is enough in mt8195. > > > > Signed-off-by: Yong Wu > > --- [...] > > struct mtk_smi { > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > { > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > - u32 reg; > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > int i; > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > return; > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > + > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > + > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > registers at the same offset? or is this unique feature for mt8195? All the other Platform's larbs have the same format at the same offset. > > > + > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > reg |= F_MMU_EN; > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > } > > } > > [...] _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu