From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH] iommu/amd: Add workaround to propery clearing IOMMU status register Date: Tue, 9 Apr 2013 19:30:30 +0200 Message-ID: <20130409173030.GH6858@8bytes.org> References: <1365031144-2543-1-git-send-email-suravee.suthikulpanit@amd.com> <20130409094929.GE6858@8bytes.org> <51642442.7090908@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <51642442.7090908-5C7GfCeVMHo@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Suravee Suthikulanit Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: iommu@lists.linux-foundation.org On Tue, Apr 09, 2013 at 09:22:58AM -0500, Suthikulpanit, Suravee wrote: > The reason I implemented the "per-thread IOMMU handling" and the > "workaround" together in one patch > is because it simplifies the synchronization of clearing and > checking the interrupt enabling bits. > In the previous implementation, we could end up having multiple > threads trying to access the status register > at the same time. This is the reason for the iommu->lock spinlock in this code at the moment. Joerg