From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability IOMMU_CAP_INTR_REMAP Date: Mon, 16 Jun 2014 17:38:32 +0200 Message-ID: <20140616153832.GC31771@8bytes.org> References: <1401987808-23596-1-git-send-email-a.motakis@virtualopensystems.com> <1401987808-23596-5-git-send-email-a.motakis@virtualopensystems.com> <20140608103129.GC3279@lvm> <20140616145344.GD18986@8bytes.org> <20140616151329.GQ16758@arm.com> <20140616152157.GB31771@8bytes.org> <20140616152526.GR16758@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20140616152526.GR16758-5wv7dgnIgG8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Will Deacon Cc: "stuart.yoder-KZfg59tc24xl57MIdRCFDg@public.gmane.org" , "kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "eric.auger-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" , open list , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "a.rigo-lrHrjnjw1UfHK3s98zE1ajGjJy/sRE9J@public.gmane.org" , "moderated list:ARM SMMU DRIVER" , Antonios Motakis , "tech-lrHrjnjw1UfHK3s98zE1ajGjJy/sRE9J@public.gmane.org" , "kvmarm-FPEHb7Xf0XXUo1n7N8X6UoWGPAHP3yOg@public.gmane.org" , Christoffer Dall List-Id: iommu@lists.linux-foundation.org On Mon, Jun 16, 2014 at 04:25:26PM +0100, Will Deacon wrote: > Ok, thanks. In which case, I think this is really a combined property of > the SMMU and the interrupt controller, so we might need some extra code > so that the SMMU can check that the interrupt controller for the device > is also capable of interrupt remapping. Right, that this is part of IOMMU code has more or less historic reasons on x86. Interrupt remapping is purely implemented in the IOMMU there, so on ARM some clue-code between interrupt controler and smmu is needed. Joerg