From: Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
To: Jerome Glisse <j.glisse-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: alexander.deucher-5C7GfCeVMHo@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
Subject: Re: IOMMU and domain binding/unbinding logic
Date: Mon, 30 Mar 2015 11:46:46 +0200 [thread overview]
Message-ID: <20150330094646.GY4441@8bytes.org> (raw)
In-Reply-To: <20150326175857.GA3196-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Jerome,
On Thu, Mar 26, 2015 at 01:58:58PM -0400, Jerome Glisse wrote:
> Of course if dev.archdata.dma_ops is pointing to nommu_dma_ops then every
> things is fine, but here i am wondering for the case where the ops are
> actualy amd_iommu_dma_ops. In the first place ie at iommu initialization
> or when hotpluging a new device (as in the hotpluging case it always set
> dev.archdata.dma_ops to amd_iommu_dma_ops AFAICT.
Yes, every device that is IOMMUv2 capable (ATS + PRI + PASID capability
present) is put into the passthrough domain at boot time. The dma_ops
point to nommu_dma_ops and after the device is used for IOMMUv2 mappings
the old DMA-API mappings remain valid.
For details you can have a look into the AMD IOMMU driver and how the
return value of pci_iommuv2_capable() is propageted.
Joerg
prev parent reply other threads:[~2015-03-30 9:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-26 16:50 IOMMU and domain binding/unbinding logic Jerome Glisse
[not found] ` <20150326165046.GA2965-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-03-26 17:09 ` Joerg Roedel
[not found] ` <20150326170935.GX4441-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2015-03-26 17:58 ` Jerome Glisse
[not found] ` <20150326175857.GA3196-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-03-30 9:46 ` Joerg Roedel [this message]
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