Linux IOMMU Development
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From: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>
To: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
Cc: "laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org"
	<laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>,
	"arnd-r2nGTMty4D4@public.gmane.org"
	<arnd-r2nGTMty4D4@public.gmane.org>,
	Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>,
	"iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org"
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
	"djkurtz-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org"
	<djkurtz-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org"
	<thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
	"yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org"
	<yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
	"treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org"
	<treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
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	<yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Subject: Re: [PATCH v3 3/4] arm64: Add IOMMU dma_ops
Date: Wed, 15 Jul 2015 17:53:16 +0100	[thread overview]
Message-ID: <20150715165316.GG20186@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <55A689EA.8030306-5wv7dgnIgG8@public.gmane.org>

On Wed, Jul 15, 2015 at 05:27:22PM +0100, Robin Murphy wrote:
> On 15/07/15 10:31, Catalin Marinas wrote:
> >On Fri, Jul 10, 2015 at 08:19:34PM +0100, Robin Murphy wrote:
> >>+			if (iommu_dma_mapping_error(dev, *handle)) {
> >>+				if (coherent)
> >>+					__free_pages(page, get_order(size));
> >>+				else
> >>+					__free_from_pool(addr, size);
> >>+				addr = NULL;
> >>+			}
> >>+		}
> >>+	}
> >>+	return addr;
> >>+}
> >
> >In the second case here (!__GFP_WAIT), do we do any cache maintenance? I
> >can't see it and it's needed for the !coherent case.
> 
> In the atomic non-coherent case, we're stealing from the atomic pool, so
> addr is already a non-cacheable alias (and alloc_from_pool does memset(0)
> through that). That shouldn't need anything extra, right?

You are right, we already flushed the cache for the atomic pool when we
allocated it in atomic_pool_init().

-- 
Catalin

  parent reply	other threads:[~2015-07-15 16:53 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-10 19:19 [PATCH v3 0/4] arm64: IOMMU-backed DMA mapping Robin Murphy
     [not found] ` <cover.1436552949.git.robin.murphy-5wv7dgnIgG8@public.gmane.org>
2015-07-10 19:19   ` [PATCH v3 1/4] iommu/iova: Avoid over-allocating when size-aligned Robin Murphy
2015-07-10 19:19   ` [PATCH v3 2/4] iommu: Implement common IOMMU ops for DMA mapping Robin Murphy
     [not found]     ` <d1a97aaee42f30370b58b3f7ed6a3559633010ad.1436552949.git.robin.murphy-5wv7dgnIgG8@public.gmane.org>
2015-07-13 12:34       ` Yong Wu
2015-07-14 17:16       ` Catalin Marinas
     [not found]         ` <20150714171640.GJ13555-M2fw3Uu6cmfZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2015-07-15 15:50           ` Robin Murphy
2015-07-10 19:19   ` [PATCH v3 3/4] arm64: Add IOMMU dma_ops Robin Murphy
     [not found]     ` <a074dfeffc8c8168bef2668de2499f072fdcfac7.1436552949.git.robin.murphy-5wv7dgnIgG8@public.gmane.org>
2015-07-15  9:31       ` Catalin Marinas
     [not found]         ` <20150715093128.GA20186-M2fw3Uu6cmfZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2015-07-15 16:27           ` Robin Murphy
     [not found]             ` <55A689EA.8030306-5wv7dgnIgG8@public.gmane.org>
2015-07-15 16:53               ` Catalin Marinas [this message]
2015-07-10 19:19   ` [PATCH v3 4/4] arm64: Hook up " Robin Murphy

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