From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH V4 4/6] perf/amd/iommu: Introduce get_iommu_bnk_cnt_evt_idx Date: Thu, 18 Feb 2016 12:45:47 +0100 Message-ID: <20160218114547.GB28866@pd.tnic> References: <1455182127-17551-1-git-send-email-Suravee.Suthikulpanit@amd.com> <1455182127-17551-5-git-send-email-Suravee.Suthikulpanit@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1455182127-17551-5-git-send-email-Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Suravee Suthikulpanit Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, peterz-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, acme-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, andihartmann-KuiJ5kEpwI6ELgA04lAiVw@public.gmane.org, mingo-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org List-Id: iommu@lists.linux-foundation.org On Thu, Feb 11, 2016 at 04:15:25PM +0700, Suravee Suthikulpanit wrote: > Introduce a helper function to calculate bit-index for assigning > performance counter assignment. > > Signed-off-by: Suravee Suthikulpanit > --- > arch/x86/events/amd/iommu.c | 19 ++++++++++++++----- > 1 file changed, 14 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c > index debf22d..812eff2 100644 > --- a/arch/x86/events/amd/iommu.c > +++ b/arch/x86/events/amd/iommu.c > @@ -145,18 +145,27 @@ static struct attribute_group amd_iommu_cpumask_group = { > > /*---------------------------------------------*/ > > +static inline > +int get_iommu_bnk_cnt_evt_idx(struct perf_amd_iommu *perf_iommu, > + int iommu_index, int bank_index, > + int cntr_index) Align args at the opening brace. > +{ > + int cntrs_per_iommu = perf_iommu->max_banks * perf_iommu->max_counters; > + int index = (perf_iommu->max_counters * bank_index) + cntr_index; > + > + return (cntrs_per_iommu * iommu_index) + index; > +} > + > static int get_next_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu) > { > unsigned long flags; > int shift, bank, cntr, retval; > - int max_banks = perf_iommu->max_banks; > - int max_cntrs = perf_iommu->max_counters; > > raw_spin_lock_irqsave(&perf_iommu->lock, flags); > > - for (bank = 0, shift = 0; bank < max_banks; bank++) { > - for (cntr = 0; cntr < max_cntrs; cntr++) { > - shift = bank + (bank*3) + cntr; > + for (bank = 0, shift = 0; bank < perf_iommu->max_banks; bank++) { Please init that shift variable above in the function entry - it confuses unnecessarily here as if it had anything to do with the loop stride. > + for (cntr = 0; cntr < perf_iommu->max_counters; cntr++) { > + shift = get_iommu_bnk_cnt_evt_idx(perf_iommu, 0, bank, cntr); \n here > if (perf_iommu->cntr_assign_mask & (1ULL< continue; > } else { > -- > 2.5.0 > > -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.