From mboxrd@z Thu Jan 1 00:00:00 1970 From: "joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org" Subject: Re: RFC: extend IOMMU attributes Date: Thu, 25 Feb 2016 15:38:55 +0100 Message-ID: <20160225143855.GD16675@8bytes.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Stuart Yoder Cc: Bharat Bhushan , "will.deacon-5wv7dgnIgG8@public.gmane.org" , Peter Newton , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , Varun Sethi , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: iommu@lists.linux-foundation.org On Thu, Feb 18, 2016 at 04:16:26PM +0000, Stuart Yoder wrote: > #define IOMMU_READ (1 << 0) > #define IOMMU_WRITE (1 << 1) > -#define IOMMU_CACHE (1 << 2) /* DMA cache coherency */ > +#define IOMMU_CACHE_COHERENT (1 << 2) /* cacheable and coherent */ > #define IOMMU_NOEXEC (1 << 3) > #define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */ > +#define IOMMU_CACHEABLE (1 << 5) /* cacheable, not coherent */ > +#define IOMMU_CACHE_ALLOCATE (1 << 6) /* hint to allocate in the cache */ Hmm, this might be a valid use-case to introduce the map_attr()/unmap_attr() calls to the IOMMU-API. I have been resistant to these functions until now because the proposed use-cases were not convincing, but for hardware-specific map-attributes like this one it could make sense. Joerg