From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Subject: Re: [PATCH v7 1/7] perf/amd/iommu: Misc fix up perf_iommu_read Date: Wed, 11 Jan 2017 12:57:35 +0100 Message-ID: <20170111115735.GI3107@twins.programming.kicks-ass.net> References: <1484019227-11473-1-git-send-email-Suravee.Suthikulpanit@amd.com> <1484019227-11473-2-git-send-email-Suravee.Suthikulpanit@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1484019227-11473-2-git-send-email-Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Suravee Suthikulpanit Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, mingo-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, bp-Gina5bIWoIWzQB+pC5nmwQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: iommu@lists.linux-foundation.org On Mon, Jan 09, 2017 at 09:33:41PM -0600, Suravee Suthikulpanit wrote: > This patch contains the following minor fixup: > * Fixed overflow handling since u64 delta would lose the MSB sign bit. Please explain.. afaict this actually introduces a bug. > diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c > index b28200d..f387baf 100644 > --- a/arch/x86/events/amd/iommu.c > +++ b/arch/x86/events/amd/iommu.c > @@ -319,29 +319,30 @@ static void perf_iommu_start(struct perf_event *event, int flags) > > static void perf_iommu_read(struct perf_event *event) > { > - u64 count = 0ULL; > - u64 prev_raw_count = 0ULL; > - u64 delta = 0ULL; > + u64 cnt, prev; > + s64 delta; > struct hw_perf_event *hwc = &event->hw; > pr_debug("perf: amd_iommu:perf_iommu_read\n"); > > amd_iommu_pc_get_set_reg_val(_GET_DEVID(event), > _GET_BANK(event), _GET_CNTR(event), > - IOMMU_PC_COUNTER_REG, &count, false); > + IOMMU_PC_COUNTER_REG, &cnt, false); > > /* IOMMU pc counter register is only 48 bits */ > - count &= 0xFFFFFFFFFFFFULL; > + cnt &= GENMASK_ULL(48, 0); > > - prev_raw_count = local64_read(&hwc->prev_count); > - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, > - count) != prev_raw_count) > - return; > + prev = local64_read(&hwc->prev_count); > > - /* Handling 48-bit counter overflowing */ > - delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT); > + /* > + * Since we do not enable counter overflow interrupts, > + * we do not have to worry about prev_count changing on us. > + */ So you cannot group this event with a software event that reads this from their sample? > + local64_set(&hwc->prev_count, cnt); > + > + /* Handle 48-bit counter overflow */ > + delta = (cnt << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); > delta >>= COUNTER_SHIFT; > local64_add(delta, &event->count); > - > } > > static void perf_iommu_stop(struct perf_event *event, int flags) > -- > 1.8.3.1 >