From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH v2 0/4] Optimise 64-bit IOVA allocations Date: Wed, 26 Jul 2017 13:08:07 +0200 Message-ID: <20170726110807.GN15833@8bytes.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Robin Murphy Cc: ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: iommu@lists.linux-foundation.org Hi Robin. On Fri, Jul 21, 2017 at 12:41:57PM +0100, Robin Murphy wrote: > Hi all, > > In the wake of the ARM SMMU optimisation efforts, it seems that certain > workloads (e.g. storage I/O with large scatterlists) probably remain quite > heavily influenced by IOVA allocation performance. Separately, Ard also > reported massive performance drops for a graphical desktop on AMD Seattle > when enabling SMMUs via IORT, which we traced to dma_32bit_pfn in the DMA > ops domain getting initialised differently for ACPI vs. DT, and exposing > the overhead of the rbtree slow path. Whilst we could go around trying to > close up all the little gaps that lead to hitting the slowest case, it > seems a much better idea to simply make said slowest case a lot less slow. Do you have some numbers here? How big was the impact before these patches and how is it with the patches? Joerg