From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH 0/4] Add support for Intel IOMMU 5-level paging Date: Wed, 17 Jan 2018 15:03:24 +0100 Message-ID: <20180117140324.6wkbi2bbt6xug53d@8bytes.org> References: <1513799967-22454-1-git-send-email-sohil.mehta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1513799967-22454-1-git-send-email-sohil.mehta-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Sohil Mehta Cc: Ravi V Shankar , Fenghua Yu , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Dave Hansen , David Woodhouse , Gayatri Kammela , Kirill Shutemov , Andy Shevchenko List-Id: iommu@lists.linux-foundation.org On Wed, Dec 20, 2017 at 11:59:23AM -0800, Sohil Mehta wrote: > Sohil Mehta (4): > iommu/vt-d: Enable upto 57 bits of domain address width > iommu/vt-d: Add a check for 1GB page support > iommu/vt-d: Add a check for 5-level paging support > iommu/vt-d: Enable 5-level paging mode in the PASID entry > > drivers/iommu/intel-iommu.c | 2 +- > drivers/iommu/intel-svm.c | 23 +++++++++++++++++++++-- > include/linux/intel-iommu.h | 2 ++ > 3 files changed, 24 insertions(+), 3 deletions(-) Applied, thanks.