From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH 12/14] dma-direct: handle the memory encryption bit in common code Date: Mon, 19 Mar 2018 16:24:42 +0100 Message-ID: <20180319152442.GA27915@lst.de> References: <20180319103826.12853-1-hch@lst.de> <20180319103826.12853-13-hch@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Robin Murphy Cc: Tom Lendacky , Konrad Rzeszutek Wilk , Catalin Marinas , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Will Deacon , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Muli Ben-Yehuda , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, David Woodhouse , Christoph Hellwig List-Id: iommu@lists.linux-foundation.org On Mon, Mar 19, 2018 at 03:19:04PM +0000, Robin Murphy wrote: > As a heads-up, I've just realised there's now a silent (but build-breaking) > conflict with the current arm64 queue brewing here, as we've unfortunately > had to reintroduce ARCH_HAS_PHYS_TO_DMA as a means of being safe against an > ugly architectural corner case - currently commit 1f85b42a691c ("arm64: > Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)") in -next. Please revert that arm64 commit. This condition should be handled in common code as it is not arm specific. And next time please CC the iommu list and dma-mapping maintainers before doing such a change.