From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jacob Pan Subject: Re: [PATCH v5 08/23] iommu/vt-d: support flushing more translation cache types Date: Mon, 14 May 2018 13:46:42 -0700 Message-ID: <20180514134642.45cdbb4d@jacob-builder> References: <1526072055-86990-1-git-send-email-jacob.jun.pan@linux.intel.com> <1526072055-86990-9-git-send-email-jacob.jun.pan@linux.intel.com> <5AF8F204.2010800@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <5AF8F204.2010800-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Lu Baolu Cc: Raj Ashok , Greg Kroah-Hartman , Rafael Wysocki , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, LKML , Jean Delvare , David Woodhouse List-Id: iommu@lists.linux-foundation.org On Mon, 14 May 2018 10:18:44 +0800 Lu Baolu wrote: > Hi, > > On 05/12/2018 04:54 AM, Jacob Pan wrote: > > When Shared Virtual Memory is exposed to a guest via vIOMMU, > > extended IOTLB invalidation may be passed down from outside IOMMU > > subsystems. This patch adds invalidation functions that can be used > > for additional translation cache types. > > > > Signed-off-by: Jacob Pan > > --- > > drivers/iommu/dmar.c | 44 > > ++++++++++++++++++++++++++++++++++++++++++++ > > include/linux/intel-iommu.h | 21 +++++++++++++++++++-- 2 files > > changed, 63 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > > index 7852678..0b5b052 100644 > > --- a/drivers/iommu/dmar.c > > +++ b/drivers/iommu/dmar.c > > @@ -1339,6 +1339,18 @@ void qi_flush_iotlb(struct intel_iommu > > *iommu, u16 did, u64 addr, qi_submit_sync(&desc, iommu); > > } > > > > +void qi_flush_eiotlb(struct intel_iommu *iommu, u16 did, u64 addr, > > u32 pasid, > > + unsigned int size_order, u64 granu, bool global) > > Alignment should match open parenthesis. > > > +{ > > + struct qi_desc desc; > > + > > + desc.low = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) | > > + QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE; > > + desc.high = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_GL(global) | > > + QI_EIOTLB_IH(0) | QI_EIOTLB_AM(size_order); > > + qi_submit_sync(&desc, iommu); > > +} > > + > > void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 > > pfsid, u16 qdep, u64 addr, unsigned mask) > > { > > @@ -1360,6 +1372,38 @@ void qi_flush_dev_iotlb(struct intel_iommu > > *iommu, u16 sid, u16 pfsid, qi_submit_sync(&desc, iommu); > > } > > > > +void qi_flush_dev_eiotlb(struct intel_iommu *iommu, u16 sid, > > + u32 pasid, u16 qdep, u64 addr, unsigned size, u64 > > granu) > > Ditto. > > > +{ > > + struct qi_desc desc; > > + > > + desc.low = QI_DEV_EIOTLB_PASID(pasid) | > > QI_DEV_EIOTLB_SID(sid) | > > + QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE; > > Have you forgotten PFSID, or I missed anything here? you are right, missed pfsid in this case. > > [...] > > Best regards, > Lu Baolu