From: Christoph Hellwig <hch-jcswGhMUV9g@public.gmane.org>
To: palmer-SpMDHPYPyPbQT0dZR+AlfA@public.gmane.org
Cc: linux-riscv-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
Subject: add swiotlb support for riscv
Date: Wed, 16 May 2018 16:42:59 +0200 [thread overview]
Message-ID: <20180516144302.823-1-hch@lst.de> (raw)
Current 64-bit RISC-V cores don't have any iommu support, so they need
iommu support when used with more than 4GB DRAM (or even just address
space depending on the SBI). This wires the support up based on
earlier patches from Palmer.
Note that the patches are on to of the dma mapping tree as they require
the swiotlb Kconfig consolidation, and should probably merged through
that tree as well.
Git tree:
git://git.infradead.org/users/hch/misc.git riscv-swiotlb
Gitweb:
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/riscv-swiotlb
next reply other threads:[~2018-05-16 14:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-16 14:42 Christoph Hellwig [this message]
[not found] ` <20180516144302.823-1-hch-jcswGhMUV9g@public.gmane.org>
2018-05-16 14:43 ` [PATCH 1/3] riscv: simplify Kconfig magic for 32-bit vs 64-bit kernels Christoph Hellwig
2018-05-16 14:43 ` [PATCH 2/3] riscv: only enable ZONE_DMA32 for 64-bit Christoph Hellwig
2018-05-16 14:43 ` [PATCH 3/3] riscv: add swiotlb support Christoph Hellwig
2018-05-18 23:31 ` add swiotlb support for riscv Palmer Dabbelt
2018-05-19 6:35 ` Christoph Hellwig
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