From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH v3 03/10] iommu/sva: Manage process address spaces Date: Tue, 25 Sep 2018 15:26:27 +0200 Message-ID: <20180925132627.vbdotr23o7lqrmnd@8bytes.org> References: <20180920170046.20154-1-jean-philippe.brucker@arm.com> <20180920170046.20154-4-jean-philippe.brucker@arm.com> <09933fce-b959-32e1-b1f3-0d4389abf735@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <09933fce-b959-32e1-b1f3-0d4389abf735-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Lu Baolu Cc: kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, Jean-Philippe Brucker , linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, liguozhu-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, christian.koenig-5C7GfCeVMHo@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org List-Id: iommu@lists.linux-foundation.org On Tue, Sep 25, 2018 at 11:15:40AM +0800, Lu Baolu wrote: > This might be problematic for vt-d (and other possible arch's which use > PASID other than SVA). When vt-d iommu works in scalable mode, a PASID > might be allocated for: > > (1) SVA > (2) Device Assignable Interface (might be a mdev or directly managed > within a device driver). > (3) SVA in VM guest > (4) Device Assignable Interface in VM guest > > So we can't expect that an io_mm pointer was associated with each PASID. > And this code might run into problem if the pasid is allocated for > usages other than SVA. So all of these use-cases above should work in parallel on the same device, just with different PASIDs? Or is a device always using only one of the above modes at the same time? Regards, Joerg