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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id a23sm10145845pfg.82.2019.12.19.16.32.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 16:32:33 -0800 (PST) From: Nicolin Chen To: thierry.reding@gmail.com, joro@8bytes.org Subject: [PATCH 2/4] iommu/tegra-smmu: Do not use PAGE_SHIFT and PAGE_MASK Date: Thu, 19 Dec 2019 16:29:12 -0800 Message-Id: <20191220002914.19043-3-nicoleotsuka@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191220002914.19043-1-nicoleotsuka@gmail.com> References: <20191220002914.19043-1-nicoleotsuka@gmail.com> Cc: linux-tegra@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, jonathanh@nvidia.com X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" PAGE_SHIFT and PAGE_MASK are defined corresponding to the page size for CPU virtual addresses, which means PAGE_SHIFT could be a number other than 12, but tegra-smmu maintains fixed 4KB IOVA pages and has fixed [21:12] bit range for PTE entries. So this patch replaces all PAGE_SHIFT/PAGE_MASK references with the macros defined with SMMU_PTE_SHIFT. Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 63a147b623e6..5594b47a88bf 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -127,6 +127,11 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) #define SMMU_PDE_SHIFT 22 #define SMMU_PTE_SHIFT 12 +#define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1)) +#define SMMU_OFFSET_IN_PAGE(x) ((unsigned long)(x) & ~SMMU_PAGE_MASK) +#define SMMU_PFN_PHYS(x) ((phys_addr_t)(x) << SMMU_PTE_SHIFT) +#define SMMU_PHYS_PFN(x) ((unsigned long)((x) >> SMMU_PTE_SHIFT)) + #define SMMU_PD_READABLE (1 << 31) #define SMMU_PD_WRITABLE (1 << 30) #define SMMU_PD_NONSECURE (1 << 29) @@ -644,7 +649,7 @@ static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, u32 *pte, dma_addr_t pte_dma, u32 val) { struct tegra_smmu *smmu = as->smmu; - unsigned long offset = offset_in_page(pte); + unsigned long offset = SMMU_OFFSET_IN_PAGE(pte); *pte = val; @@ -680,7 +685,7 @@ static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, pte_attrs |= SMMU_PTE_WRITABLE; tegra_smmu_set_pte(as, iova, pte, pte_dma, - __phys_to_pfn(paddr) | pte_attrs); + SMMU_PHYS_PFN(paddr) | pte_attrs); return 0; } @@ -716,7 +721,7 @@ static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, pfn = *pte & as->smmu->pfn_mask; - return PFN_PHYS(pfn); + return SMMU_PFN_PHYS(pfn); } static struct tegra_smmu *tegra_smmu_find(struct device_node *np) @@ -1034,7 +1039,8 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev, smmu->dev = dev; smmu->mc = mc; - smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; + smmu->pfn_mask = + BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", mc->soc->num_address_bits, smmu->pfn_mask); smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1; -- 2.17.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu