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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id q21sm9268767pgl.7.2020.05.11.22.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2020 22:52:45 -0700 (PDT) Date: Mon, 11 May 2020 22:52:42 -0700 From: Bjorn Andersson To: Shawn Guo Subject: Re: [PATCH] iommu/qcom: add optional clock for TLB invalidate Message-ID: <20200512055242.GJ1302550@yoga> References: <20200509130825.28248-1-shawn.guo@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200509130825.28248-1-shawn.guo@linaro.org> Cc: linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org, Konrad Dybcio , Andy Gross X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Sat 09 May 06:08 PDT 2020, Shawn Guo wrote: > On some SoCs like MSM8939 with A405 adreno, there is a gfx_tbu clock > needs to be on while doing TLB invalidate. Otherwise, TLBSYNC status > will not be correctly reflected, causing the system to go into a bad > state. Add it as an optional clock, so that platforms that have this > clock can pass it over DT. > > Signed-off-by: Shawn Guo > --- > drivers/iommu/qcom_iommu.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c > index 0e2a96467767..2f6c6da7d540 100644 > --- a/drivers/iommu/qcom_iommu.c > +++ b/drivers/iommu/qcom_iommu.c > @@ -45,6 +45,7 @@ struct qcom_iommu_dev { > struct device *dev; > struct clk *iface_clk; > struct clk *bus_clk; > + struct clk *tlb_clk; > void __iomem *local_base; > u32 sec_id; > u8 num_ctxs; > @@ -643,11 +644,20 @@ static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu) > return ret; > } > > + ret = clk_prepare_enable(qcom_iommu->tlb_clk); > + if (ret) { > + dev_err(qcom_iommu->dev, "Couldn't enable tlb_clk\n"); > + clk_disable_unprepare(qcom_iommu->bus_clk); > + clk_disable_unprepare(qcom_iommu->iface_clk); > + return ret; > + } Seems this is an excellent opportunity to replace qcom_iommu_enable_clocks() to clk_bulk_prepare_enable() and disable, respectively. > + > return 0; > } > > static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu) > { > + clk_disable_unprepare(qcom_iommu->tlb_clk); > clk_disable_unprepare(qcom_iommu->bus_clk); > clk_disable_unprepare(qcom_iommu->iface_clk); > } > @@ -839,6 +849,12 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) > return PTR_ERR(qcom_iommu->bus_clk); > } > > + qcom_iommu->tlb_clk = devm_clk_get(dev, "tlb"); Wouldn't "tbu" be a better name for this clock? Given that seems the actually be the hardware block you're clocking. That said, I thought we used device links and pm_runtime to ensure that the TBUs are powered and clocked... Regards, Bjorn > + if (IS_ERR(qcom_iommu->tlb_clk)) { > + dev_dbg(dev, "failed to get tlb clock\n"); > + qcom_iommu->tlb_clk = NULL; > + } > + > if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id", > &qcom_iommu->sec_id)) { > dev_err(dev, "missing qcom,iommu-secure-id property\n"); > -- > 2.17.1 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu