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Thu, 14 May 2020 07:39:16 -0700 (PDT) Received: from dragon ([80.251.214.228]) by smtp.gmail.com with ESMTPSA id w2sm18702332pja.53.2020.05.14.07.39.12 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 May 2020 07:39:15 -0700 (PDT) Date: Thu, 14 May 2020 22:39:06 +0800 From: Shawn Guo To: Bjorn Andersson Subject: Re: [PATCH] iommu/qcom: add optional clock for TLB invalidate Message-ID: <20200514143905.GA10507@dragon> References: <20200509130825.28248-1-shawn.guo@linaro.org> <20200512055242.GJ1302550@yoga> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200512055242.GJ1302550@yoga> User-Agent: Mutt/1.9.4 (2018-02-28) Cc: linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org, Konrad Dybcio , Andy Gross X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Bjorn, On Mon, May 11, 2020 at 10:52:42PM -0700, Bjorn Andersson wrote: > On Sat 09 May 06:08 PDT 2020, Shawn Guo wrote: > > > On some SoCs like MSM8939 with A405 adreno, there is a gfx_tbu clock > > needs to be on while doing TLB invalidate. Otherwise, TLBSYNC status > > will not be correctly reflected, causing the system to go into a bad > > state. Add it as an optional clock, so that platforms that have this > > clock can pass it over DT. > > > > Signed-off-by: Shawn Guo > > --- > > drivers/iommu/qcom_iommu.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c > > index 0e2a96467767..2f6c6da7d540 100644 > > --- a/drivers/iommu/qcom_iommu.c > > +++ b/drivers/iommu/qcom_iommu.c > > @@ -45,6 +45,7 @@ struct qcom_iommu_dev { > > struct device *dev; > > struct clk *iface_clk; > > struct clk *bus_clk; > > + struct clk *tlb_clk; > > void __iomem *local_base; > > u32 sec_id; > > u8 num_ctxs; > > @@ -643,11 +644,20 @@ static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu) > > return ret; > > } > > > > + ret = clk_prepare_enable(qcom_iommu->tlb_clk); > > + if (ret) { > > + dev_err(qcom_iommu->dev, "Couldn't enable tlb_clk\n"); > > + clk_disable_unprepare(qcom_iommu->bus_clk); > > + clk_disable_unprepare(qcom_iommu->iface_clk); > > + return ret; > > + } > > Seems this is an excellent opportunity to replace > qcom_iommu_enable_clocks() to clk_bulk_prepare_enable() and disable, > respectively. So we have two required and one optional clocks. I guess we don't want to use clk_bulk_get_optional() to get all of them as optional. So we will end up with getting clock with individual call and enabling/disabling with bulk version. I'm personally not fond of this mixed style. But if you really like this, I can change. > > > + > > return 0; > > } > > > > static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu) > > { > > + clk_disable_unprepare(qcom_iommu->tlb_clk); > > clk_disable_unprepare(qcom_iommu->bus_clk); > > clk_disable_unprepare(qcom_iommu->iface_clk); > > } > > @@ -839,6 +849,12 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) > > return PTR_ERR(qcom_iommu->bus_clk); > > } > > > > + qcom_iommu->tlb_clk = devm_clk_get(dev, "tlb"); > > Wouldn't "tbu" be a better name for this clock? Given that seems the > actually be the hardware block you're clocking. I was trying to emphasize the function of this clock. But I agree that 'tbu' is a better name now. I will change it in v2. Thanks for the comments. Shawn _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu