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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id y18sm662361pff.10.2020.06.29.16.52.54 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Jun 2020 16:52:55 -0700 (PDT) Date: Mon, 29 Jun 2020 16:52:20 -0700 From: Nicolin Chen To: Krishna Reddy Subject: Re: [PATCH v7 1/3] iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage Message-ID: <20200629235219.GA14616@Asurada-Nvidia> References: <20200629022838.29628-1-vdumpa@nvidia.com> <20200629022838.29628-2-vdumpa@nvidia.com> <20200629215124.GD27967@Asurada-Nvidia> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Cc: Sachin Nikam , Mikko Perttunen , Bryan Huntsman , "will@kernel.org" , "linux-kernel@vger.kernel.org" , Pritesh Raithatha , Timo Alho , "iommu@lists.linux-foundation.org" , Nicolin Chen , "linux-tegra@vger.kernel.org" , Yu-Huan Hsu , Thierry Reding , "robin.murphy@arm.com" , "linux-arm-kernel@lists.infradead.org" , Bitan Biswas X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, Jun 29, 2020 at 10:49:31PM +0000, Krishna Reddy wrote: > >> + if (!nvidia_smmu->bases[0]) > >> + nvidia_smmu->bases[0] = smmu->base; > >> + > >> + return nvidia_smmu->bases[inst] + (page << smmu->pgshift); } > > >Not critical -- just a nit: why not put the bases[0] in init()? > > smmu->base is not available during nvidia_smmu_impl_init() call. It is set afterwards in arm-smmu.c. > It can't be avoided without changing the devm_ioremap() and impl_init() call order in arm-smmu.c. I see...just checked arm_ssmu_impl_init(). _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu