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Sat, 18 Jul 2020 19:35:08 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 18 Jul 2020 19:35:07 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 18 Jul 2020 12:35:07 -0700 From: Krishna Reddy To: , , , , , Subject: [PATCH v11 1/5] iommu/arm-smmu: move TLB timeout and spin count macros Date: Sat, 18 Jul 2020 12:34:53 -0700 Message-ID: <20200718193457.30046-2-vdumpa@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200718193457.30046-1-vdumpa@nvidia.com> References: <20200718193457.30046-1-vdumpa@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595100794; bh=qPS2Zde0PkvVJILigsJkjD3Do3jtE9kFjxO2xm+rwAI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=M9rbBpaEoRYm8EV2DiOWt9d9YwENtbZkmGs//oEHYoU9c3iNQWLAiBE/CFo9Vah1Y emZRVNQgaIK85moYVKKQvBdpF2k/UzMnIAC5BasTCSm5HiZml0a6bIrBRjIQGSAiqZ 5z820WELHgI9Jr2fl97Xr17mSqhR+JuaN8HDkHXrKxNGTsdEySXdyqf+LvYXb/cZdS 1Y5xOdmrI3hGOg+q1Gr8EXPIEE0E3wWj7ncfGWEvK3QOwUgBjPZ3naufiUg//rZEsU WLfk1F+qewRrE0w/ckH4XOqcQqd5WdWsjnORQE8J3EnyJSxYAdsbAhM+0HUS79mowU eAo2tCpALigUA== Cc: snikam@nvidia.com, devicetree@vger.kernel.org, mperttunen@nvidia.com, bhuntsman@nvidia.com, yhsu@nvidia.com, linux-kernel@vger.kernel.org, talho@nvidia.com, iommu@lists.linux-foundation.org, Thierry Reding , nicolinc@nvidia.com, linux-tegra@vger.kernel.org, praithatha@nvidia.com, linux-arm-kernel@lists.infradead.org, bbiswas@nvidia.com X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Move TLB timeout and spin count macros to header file to allow using the same from vendor specific implementations. Reviewed-by: Jon Hunter Reviewed-by: Nicolin Chen Reviewed-by: Pritesh Raithatha Reviewed-by: Robin Murphy Reviewed-by: Thierry Reding Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu.c | 3 --- drivers/iommu/arm-smmu.h | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 19f906de6420..cdd15ead9bc4 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -52,9 +52,6 @@ */ #define QCOM_DUMMY_VAL -1 -#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ -#define TLB_SPIN_COUNT 10 - #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index d172c024be61..c7d0122a7c6c 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -236,6 +236,8 @@ enum arm_smmu_cbar_type { /* Maximum number of context banks per SMMU */ #define ARM_SMMU_MAX_CBS 128 +#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ +#define TLB_SPIN_COUNT 10 /* Shared driver definitions */ enum arm_smmu_arch_version { -- 2.26.2 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu