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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id a2sm21698033pfg.120.2020.07.21.16.58.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2020 16:58:44 -0700 (PDT) Date: Tue, 21 Jul 2020 16:56:50 -0700 From: Bjorn Andersson To: Konrad Dybcio Subject: Re: [PATCH 1/1] iommu/arm-smmu: Implement qcom,skip-init Message-ID: <20200721235650.GN388985@builder.lan> References: <20200704122809.73794-1-konradybcio@gmail.com> <20200704130922.GB21333@willie-the-truck> <20200705033511.GR388985@builder.lan> <20200721154415.GA5758@jcrouse1-lnx.qualcomm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: DTML , skrzynka@konradybcio.pl, Will Deacon , Linux Kernel Mailing List , iommu@lists.linux-foundation.org, Rob Herring , John Stultz , Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Tue 21 Jul 09:20 PDT 2020, Konrad Dybcio wrote: > >The current > >focus has been on moving more of the SMMU specific bits into the arm-smmu-qcom > >implementation [1] and I think that is the right way to go. > > Pardon if I overlooked something obvious, but I can't seem to find a > clean way for implementing qcom,skip-init in arm-smmu-qcom, as neither > the arm_smmu_test_smr_masks nor the probe function seem to be > alterable with arm_smmu_impl. I'm open to your ideas guys. > Is the problem on SDM630 that when you write to SMR/S2CR the device reboots? Or that when you start writing out the context bank configuration that trips the display and the device reboots? Regards, Bjorn _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu