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Fri, 02 Oct 2020 04:10:18 -0700 (PDT) Received: from pi3 ([194.230.155.194]) by smtp.googlemail.com with ESMTPSA id v25sm906385edr.29.2020.10.02.04.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2020 04:10:17 -0700 (PDT) Date: Fri, 2 Oct 2020 13:10:14 +0200 From: Krzysztof Kozlowski To: Yong Wu Subject: Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU Message-ID: <20201002111014.GE6888@pi3> References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-7-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200930070647.10188-7-yong.wu@mediatek.com> Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, kernel-team@android.com, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, Robin Murphy , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > This patch adds decriptions for mt8192 IOMMU and SMI. > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > table format. The M4U-SMI HW diagram is as below: > > EMI > | > M4U > | > ------------ > SMI Common > ------------ > | > +-------+------+------+----------------------+-------+ > | | | | ...... | | > | | | | | | > larb0 larb1 larb2 larb4 ...... larb19 larb20 > disp0 disp1 mdp vdec IPE IPE > > All the connections are HW fixed, SW can NOT adjust it. > > mt8192 M4U support 0~16GB iova range. we preassign different engines > into different iova ranges: > > domain-id module iova-range larbs > 0 disp 0 ~ 4G larb0/1 > 1 vcodec 4G ~ 8G larb4/5/7 > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 > > The iova range for CCU0/1(camera control unit) is HW requirement. > > Signed-off-by: Yong Wu > Reviewed-by: Rob Herring > --- > .../bindings/iommu/mediatek,iommu.yaml | 9 +- > .../mediatek,smi-common.yaml | 5 +- > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++ > 4 files changed, 251 insertions(+), 5 deletions(-) > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h I see it depends on previous patches but does it have to be within one commit? Is it not bisectable? The memory changes/bindings could go via memory tree if this is split. Best regards, Krzysztof _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu