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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id e47sm2643616ote.50.2020.11.03.10.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2020 10:13:03 -0800 (PST) Date: Tue, 3 Nov 2020 12:13:01 -0600 From: Bjorn Andersson To: Robin Murphy Subject: Re: [PATCH v18 2/4] iommu/arm-smmu: Add a way for implementations to influence SCTLR Message-ID: <20201103181301.GR3151@builder.lan> References: <20201102171416.654337-1-jcrouse@codeaurora.org> <20201102171416.654337-3-jcrouse@codeaurora.org> <0a00c162-ad77-46b7-85ad-e11229b57a3d@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <0a00c162-ad77-46b7-85ad-e11229b57a3d@arm.com> Cc: Rob Clark , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org, Stephen Boyd , Vivek Gautam , Greg Kroah-Hartman , Thierry Reding , Will Deacon , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon 02 Nov 12:18 CST 2020, Robin Murphy wrote: > On 2020-11-02 17:14, Jordan Crouse wrote: > > From: Rob Clark > > > > For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that > > pending translations are not terminated on iova fault. Otherwise > > a terminated CP read could hang the GPU by returning invalid > > command-stream data. > > > > Signed-off-by: Rob Clark > > Reviewed-by: Bjorn Andersson > > Signed-off-by: Jordan Crouse > > --- > > > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++ > > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ > > drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ > > 3 files changed, 12 insertions(+) > > > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > > index 1e942eed2dfc..0663d7d26908 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > > @@ -129,6 +129,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > + /* > > + * On the GPU device we want to process subsequent transactions after a > > + * fault to keep the GPU from hanging > > + */ > > + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF; > > + > > /* > > * Initialize private interface with GPU: > > */ > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > > index dad7fa86fbd4..1f06ab219819 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > > @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) > > if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) > > reg |= ARM_SMMU_SCTLR_E; > > + reg |= cfg->sctlr_set; > > + reg &= ~cfg->sctlr_clr; > > Since we now have a write_s2cr hook, I'm inclined to think that the > consistency of a write_sctlr hook that could similarly apply its own > arbitrary tweaks would make sense for this. Does anyone have any strong > opinions? > I like it. Regards, Bjorn > Robin. > > > + > > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > > } > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > > index 6c5ff9999eae..ddf2ca4c923d 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > > @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { > > #define ARM_SMMU_CB_SCTLR 0x0 > > #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) > > #define ARM_SMMU_SCTLR_CFCFG BIT(7) > > +#define ARM_SMMU_SCTLR_HUPCF BIT(8) > > #define ARM_SMMU_SCTLR_CFIE BIT(6) > > #define ARM_SMMU_SCTLR_CFRE BIT(5) > > #define ARM_SMMU_SCTLR_E BIT(4) > > @@ -341,6 +342,8 @@ struct arm_smmu_cfg { > > u16 asid; > > u16 vmid; > > }; > > + u32 sctlr_set; /* extra bits to set in SCTLR */ > > + u32 sctlr_clr; /* bits to mask in SCTLR */ > > enum arm_smmu_cbar_type cbar; > > enum arm_smmu_context_fmt fmt; > > }; > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu