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Thu, 25 Mar 2021 06:03:16 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id h9sm6317280wmb.35.2021.03.25.06.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Mar 2021 06:03:14 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Will Deacon , Robin Murphy , Joerg Roedel , Krzysztof Kozlowski Subject: [PATCH 0/9] arm64: tegra: Prevent early SMMU faults Date: Thu, 25 Mar 2021 14:03:23 +0100 Message-Id: <20210325130332.778208-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Cc: iommu@lists.linux-foundation.org, Jon Hunter , Nicolin Chen , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" From: Thierry Reding Hi, this is a set of patches that is the result of earlier discussions regarding early identity mappings that are needed to avoid SMMU faults during early boot. The goal here is to avoid early identity mappings altogether and instead postpone the need for the identity mappings to when devices are attached to the SMMU. This works by making the SMMU driver coordinate with the memory controller driver on when to start enforcing SMMU translations. This makes Tegra behave in a more standard way and pushes the code to deal with the Tegra-specific programming into the NVIDIA SMMU implementation. Patches 1 and 2 are preparatory work that is used in patch 3 to provide a mechanism to program SID overrides at runtime. Patches 4 and 5 create the fundamentals in the SMMU driver to support this and also make this functionality available on Tegra186. Patch 6 hooks the ARM SMMU up to the memory controller so that the memory overrides can be programmed at the right time. Patch 7 extends this mechanism to Tegra186 and patches 8-9 enable all of this through device tree updates. The end result is that various peripherals will have SMMU enabled, while the display controllers will keep using passthrough, as initially set up by firmware. Once the device tree bindings have been accepted and the SMMU driver has been updated to create identity mappings for the display controllers, they can be hooked up to the SMMU and the code in this series will automatically program the SID overrides to enable SMMU translations at the right time. Thierry Thierry Reding (9): memory: tegra: Move internal data structures into separate header memory: tegra: Add memory client IDs to tables memory: tegra: Implement SID override programming iommu/arm-smmu: Implement ->probe_finalize() iommu/arm-smmu: tegra: Detect number of instances at runtime iommu/arm-smmu: tegra: Implement SID override programming iommu/arm-smmu: Use Tegra implementation on Tegra186 arm64: tegra: Hook up memory controller to SMMU on Tegra186 arm64: tegra: Enable SMMU support on Tegra194 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 86 ++++++ drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 +- drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 81 ++++-- drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 ++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + drivers/iommu/tegra-gart.c | 2 +- drivers/iommu/tegra-smmu.c | 2 +- drivers/memory/tegra/mc.h | 2 +- drivers/memory/tegra/tegra186.c | 288 ++++++++++++++++++- include/soc/tegra/mc-internal.h | 62 ++++ include/soc/tegra/mc.h | 60 +--- 12 files changed, 529 insertions(+), 77 deletions(-) create mode 100644 include/soc/tegra/mc-internal.h -- 2.30.2 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu