From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 939D7C433EF for ; Fri, 17 Dec 2021 22:02:01 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 469FF6118C; Fri, 17 Dec 2021 22:02:01 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Fc6HhbCACkJM; Fri, 17 Dec 2021 22:02:00 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [IPv6:2605:bc80:3010:104::8cd3:938]) by smtp3.osuosl.org (Postfix) with ESMTPS id 23AD361188; Fri, 17 Dec 2021 22:02:00 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id A5200C0073; Fri, 17 Dec 2021 22:01:59 +0000 (UTC) Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists.linuxfoundation.org (Postfix) with ESMTP id 7BDB6C002F for ; Fri, 17 Dec 2021 22:01:58 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 5B6C96117D for ; Fri, 17 Dec 2021 22:01:58 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eX82d3DtuxMe for ; Fri, 17 Dec 2021 22:01:57 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.8.0 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by smtp3.osuosl.org (Postfix) with ESMTPS id 4EE1561147 for ; Fri, 17 Dec 2021 22:01:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778517; x=1671314517; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=0jm2eAYVlDkuiCKKJYYzdwdod6o9ZLQ3TVZ+0dw78z8=; b=nYoxR4ClbVOzrh+MGF83mW75aJoGltwaDAMqbKp6qsU3W2a/CH9YHBRs 26RczxhW4tq8XJa9UdXG9z1r+D+nG6R48xcTt/2eJTwGJ9ACkDwANd2je pFpb4ogw7BXQAd1jSe7ocvo0OzNjHM1TonJ1w4lZ3S4fu6w0cPFbfQSUw 9kAIv9gUYAAMRGRozPMdIIilX/IkUBFisHalSLxzzdtosBGMsTnz+MkA3 eMRvhNDjdvakxbM2q13lv/W3ycNYPnZ2QcvM+ZdJX4gAsyIX4Ml0ErhJQ orqst99AfrQbEex101jT0LJtd8ZJ1Fr0/mkfLN1i8W5IWIxlaFoX75zXd Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="239793557" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="239793557" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928069" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:46 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Subject: [PATCH v2 00/11] Re-enable ENQCMD and PASID MSR Date: Fri, 17 Dec 2021 22:01:25 +0000 Message-Id: <20211217220136.2762116-1-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Cc: Fenghua Yu , iommu@lists.linux-foundation.org, x86 , linux-kernel X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Problems in the old code to manage SVM (Shared Virtual Memory) devices and the PASID (Process Address Space ID) led to that code being disabled. Subsequent discussions resulted in a far simpler approach: 1) PASID life cycle is from first allocation by a process until that process exits. 2) All tasks begin with PASID disabled 3) The #GP fault handler tries to fix faulting ENQCMD instructions very early (thus avoiding complexities of the XSAVE infrastructure) Change Log: v2: - Free PASID on mm exit instead of in exit(2) or unbind() (Thomas, AndyL, PeterZ) - Directly write IA32_PASID MSR in fixup while local IRQ is still disabled (Thomas) - Simplify handling ENQCMD in objtool (PeterZ and Josh) - Define mm_pasid_get(), mm_pasid_drop(), and mm_pasid_init() in mm and call the functions from IOMMU (Dave Hansen). - A few changes in the #GP fixup function (Dave Hansen, Tony Luck). - Initial PASID value is changed to INVALID_PASID (Ashok Raj and Jacob Pan). - Add mm_pasid_init(), mm_pasid_get(), and mm_pasid_drop() functions in mm. So the mm's PASID operations are generic for both X86 and ARM (Dave Hansen). - Rename CONFIG_IOMMU_SVA_LIB to more useful and accurate CONFIG_IOMMU_SVA - Use CONFIG_IOMMU_SVA for PASID processing condition (Jacob) - The patch that cleans up old update_pasid() function is in upstream now (commit: 00ecd5401349 "iommu/vt-d: Clean up unused PASID updating functions") and therefore it's removed from this version. v1 can be found at https://lore.kernel.org/lkml/20210920192349.2602141-1-fenghua.yu@intel.com/T/#md6d542091da1d1159eda0a44a16e57d0c0dfb209 Fenghua Yu (10): iommu/sva: Rename CONFIG_IOMMU_SVA_LIB to CONFIG_IOMMU_SVA mm: Change CONFIG option for mm->pasid field iommu/ioasid: Introduce a helper to check for valid PASIDs kernel/fork: Initialize mm's PASID iommu/sva: Assign a PASID to mm on PASID allocation and free it on mm exit x86/fpu: Clear PASID when copying fpstate x86/traps: Demand-populate PASID MSR via #GP x86/cpufeatures: Re-enable ENQCMD tools/objtool: Check for use of the ENQCMD instruction in the kernel docs: x86: Change documentation for SVA (Shared Virtual Addressing) Peter Zijlstra (1): sched: Define and initialize a flag to identify valid PASID in the task Documentation/x86/sva.rst | 58 +++++++++++++++---- arch/x86/include/asm/disabled-features.h | 7 ++- arch/x86/kernel/fpu/core.c | 7 +++ arch/x86/kernel/traps.c | 55 ++++++++++++++++++ drivers/iommu/Kconfig | 6 +- drivers/iommu/Makefile | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +- drivers/iommu/intel/Kconfig | 2 +- drivers/iommu/intel/svm.c | 9 --- drivers/iommu/iommu-sva-lib.c | 39 ++++--------- drivers/iommu/iommu-sva-lib.h | 7 +-- include/linux/ioasid.h | 9 +++ include/linux/mm_types.h | 2 +- include/linux/sched.h | 3 + include/linux/sched/mm.h | 26 +++++++++ kernel/fork.c | 15 +++-- mm/init-mm.c | 4 ++ tools/objtool/arch/x86/decode.c | 11 +++- 18 files changed, 194 insertions(+), 73 deletions(-) -- 2.34.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu