From: Alex Deucher via iommu <iommu@lists.linux-foundation.org>
To: <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<corbet@lwn.net>, <hpa@zytor.com>, <x86@kernel.org>,
<dave.hansen@linux.intel.com>, <bp@alien8.de>, <mingo@redhat.com>,
<tglx@linutronix.de>, <joro@8bytes.org>,
<suravee.suthikulpanit@amd.com>, <will@kernel.org>,
<iommu@lists.linux-foundation.org>, <robin.murphy@arm.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 2/2] Documentation: x86: Clarify Intel IOMMU documenation
Date: Wed, 9 Mar 2022 12:58:05 -0500 [thread overview]
Message-ID: <20220309175805.1298503-2-alexander.deucher@amd.com> (raw)
In-Reply-To: <20220309175805.1298503-1-alexander.deucher@amd.com>
Based on feedback from Robin on the initial AMD IOMMU
documentation, fix up the Intel documentation to
clarify IOMMU vs device and modern DMA API.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
Documentation/x86/intel-iommu.rst | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/x86/intel-iommu.rst b/Documentation/x86/intel-iommu.rst
index 4d3391c7bd3f..22e1934a1335 100644
--- a/Documentation/x86/intel-iommu.rst
+++ b/Documentation/x86/intel-iommu.rst
@@ -19,8 +19,8 @@ Some Keywords
Basic stuff
-----------
-ACPI enumerates and lists the different DMA engines in the platform, and
-device scope relationships between PCI devices and which DMA engine controls
+ACPI enumerates and lists the different IOMMUs in the platform, and
+device scope relationships between PCI devices and which IOMMU controls
them.
What is RMRR?
@@ -36,9 +36,9 @@ unity mappings for these regions for these devices to access these regions.
How is IOVA generated?
----------------------
-Well behaved drivers call pci_map_*() calls before sending command to device
+Well behaved drivers call dma_map_*() calls before sending command to device
that needs to perform DMA. Once DMA is completed and mapping is no longer
-required, device performs a pci_unmap_*() calls to unmap the region.
+required, device performs a dma_unmap_*() calls to unmap the region.
The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
device has its own domain (hence protection). Devices under p2p bridges
@@ -68,7 +68,7 @@ address from PCI MMIO ranges so they are not allocated for IOVA addresses.
Fault reporting
---------------
-When errors are reported, the DMA engine signals via an interrupt. The fault
+When errors are reported, the IOMMU signals via an interrupt. The fault
reason and device that caused it with fault reason is printed on console.
See below for sample.
--
2.35.1
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next prev parent reply other threads:[~2022-03-09 17:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 17:58 [PATCH v2 1/2] Documentation: x86: Add documenation for AMD IOMMU Alex Deucher via iommu
2022-03-09 17:58 ` Alex Deucher via iommu [this message]
2022-03-09 18:36 ` [PATCH 2/2] Documentation: x86: Clarify Intel IOMMU documenation Dave Hansen
2022-03-10 4:17 ` [PATCH v2 1/2] Documentation: x86: Add documenation for AMD IOMMU Vasant Hegde via iommu
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