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Mon, 11 Apr 2022 00:31:32 -0700 (PDT) Received: from thinkpad ([117.217.182.106]) by smtp.gmail.com with ESMTPSA id a9-20020a056a000c8900b004fb37ecc6bbsm35321318pfv.65.2022.04.11.00.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 00:31:32 -0700 (PDT) Date: Mon, 11 Apr 2022 13:01:24 +0530 From: Manivannan Sadhasivam To: Rohit Agarwal Subject: Re: [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller Message-ID: <20220411073124.GC24975@thinkpad> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> <1649660143-22400-4-git-send-email-quic_rohiagar@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1649660143-22400-4-git-send-email-quic_rohiagar@quicinc.com> Cc: devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-kernel@vger.kernel.org, will@kernel.org, linux-mmc@vger.kernel.org, agross@kernel.org, iommu@lists.linux-foundation.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, krzk+dt@kernel.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, Apr 11, 2022 at 12:25:39PM +0530, Rohit Agarwal wrote: > Add devicetree support for SDHCI controller found in Qualcomm SDX65 > platform. The SDHCI controller is based on the MSM SDHCI v5 IP. > > Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 365df74..632ac78 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -168,6 +168,19 @@ > #interrupt-cells = <2>; > }; > > + sdhc_1: sdhci@8804000 { > + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x08804000 0x1000>; > + reg-names = "hc_mem"; > + interrupts = , > + ; > + interrupt-names = "hc_irq", "pwr_irq"; > + clocks = <&gcc GCC_SDCC1_APPS_CLK>, > + <&gcc GCC_SDCC1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > pdc: interrupt-controller@b210000 { > compatible = "qcom,sdx65-pdc", "qcom,pdc"; > reg = <0xb210000 0x10000>; > -- > 2.7.4 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu