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Mon, 11 Apr 2022 00:32:56 -0700 (PDT) Received: from thinkpad ([117.217.182.106]) by smtp.gmail.com with ESMTPSA id x6-20020a056a000bc600b005058a09f3aesm10186371pfu.147.2022.04.11.00.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 00:32:55 -0700 (PDT) Date: Mon, 11 Apr 2022 13:02:46 +0530 From: Manivannan Sadhasivam To: Rohit Agarwal Subject: Re: [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Message-ID: <20220411073246.GD24975@thinkpad> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> <1649660143-22400-6-git-send-email-quic_rohiagar@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1649660143-22400-6-git-send-email-quic_rohiagar@quicinc.com> Cc: devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-kernel@vger.kernel.org, will@kernel.org, linux-mmc@vger.kernel.org, agross@kernel.org, iommu@lists.linux-foundation.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, krzk+dt@kernel.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, Apr 11, 2022 at 12:25:41PM +0530, Rohit Agarwal wrote: > Add a node for the ARM SMMU found in the SDX65. > > Signed-off-by: Rohit Agarwal > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 632ac78..2481769 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -181,6 +181,46 @@ > status = "disabled"; > }; > > + apps_smmu: iommu@15000000 { Please sort the nodes in ascending order. Thanks, Mani > + compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; > + reg = <0x15000000 0x40000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > pdc: interrupt-controller@b210000 { > compatible = "qcom,sdx65-pdc", "qcom,pdc"; > reg = <0xb210000 0x10000>; > -- > 2.7.4 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu