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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q19-20020a4a8353000000b00333220959b9sm1265718oog.1.2022.05.18.11.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 May 2022 11:43:40 -0700 (PDT) Received: (nullmailer pid 3669786 invoked by uid 1000); Wed, 18 May 2022 18:43:39 -0000 Date: Wed, 18 May 2022 13:43:39 -0500 From: Rob Herring To: AngeloGioacchino Del Regno Subject: Re: [PATCH 7/8] dt-bindings: iommu: mediatek: Require mediatek,infracfg for mt2712/8173 Message-ID: <20220518184339.GJ3302100-robh@kernel.org> References: <20220517132107.195932-1-angelogioacchino.delregno@collabora.com> <20220517132107.195932-8-angelogioacchino.delregno@collabora.com> <20220518014143.GA2024242-robh@kernel.org> <4ed63c3a-ec47-5801-ab89-b7d1a597c0da@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4ed63c3a-ec47-5801-ab89-b7d1a597c0da@collabora.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, will@kernel.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, May 18, 2022 at 10:14:43AM +0200, AngeloGioacchino Del Regno wrote: > Il 18/05/22 03:41, Rob Herring ha scritto: > > On Tue, May 17, 2022 at 03:21:06PM +0200, AngeloGioacchino Del Regno wrote: > > > Both MT2712 and MT8173 got a mediatek,infracfg phandle: add that to > > > the required properties for these SoCs to deprecate the old way of > > > looking for SoC-specific infracfg compatible in the entire devicetree. > > > > Wait, what? If there's only one possible node that can match, I prefer > > the 'old way'. Until we implemented a phandle cache, searching the > > entire tree was how phandle lookups worked too, so not any better. > > > > But if this makes things more consistent, > > > > Acked-by: Rob Herring > > > Hello Rob, > > This makes things definitely more consistent, as it's done like that on > mtk-pm-domains and other mtk drivers as well. > > The main reason why this phandle is useful, here and in other drivers, is > that we're seeing a list of compatibles that is growing more and more, so > you see stuff like (mockup names warning): > > switch (some_model) > case MT1000: > p = "mediatek,mt1000-infracfg"; > break; > case MT1001: > p = "mediatek,mt1001-infracfg"; > break; > case MT1002: > p = "mediatek,mt1002-infracfg"; > break; > .....add another 20 SoCs, replicate this switch for 4/5 drivers.... This type of property is used for poking random bits in another block (that's usually a collection of random bits). These interfaces don't tend to be that stable across many SoC generations. As there's no abstraction beyond perhaps what the offset is, the client side ends up needing to know the specifics of that block anyways. If the block is that stable, then perhaps it needs a common fallback compatible. Sometimes these instances are also just places we haven't created a common subsystem for. > and this is why I want the mtk_iommu driver to also get that phandle like > some other drivers are already doing. As I said, fine. Rob _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu