From: Vasant Hegde <vasant.hegde@amd.com>
To: <joro@8bytes.org>, <iommu@lists.linux.dev>
Cc: <suravee.suthikulpanit@amd.com>, <robin.murphy@arm.com>,
Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH v2 5/6] iommu/amd: Add support for using AMD IOMMU v2 page table for DMA-API
Date: Wed, 13 Jul 2022 11:00:33 +0530 [thread overview]
Message-ID: <20220713053034.12061-6-vasant.hegde@amd.com> (raw)
In-Reply-To: <20220713053034.12061-1-vasant.hegde@amd.com>
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Introduce init function for setting up DMA domain for DMA-API with
the IOMMU v2 page table.
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
Changes in v2:
- Added support to change supported page sizes dynamically based on domain type.
drivers/iommu/amd/iommu.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 2e67e6eecc31..372621dfc526 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1642,6 +1642,10 @@ static void do_attach(struct iommu_dev_data *dev_data,
domain->dev_iommu[iommu->index] += 1;
domain->dev_cnt += 1;
+ /* Override supported page sizes */
+ if (domain->flags & PD_GIOV_MASK)
+ domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
+
/* Update device table */
set_dte_entry(iommu, dev_data->devid, domain,
ats, dev_data->iommu_v2);
@@ -2021,6 +2025,24 @@ static int protection_domain_init_v1(struct protection_domain *domain, int mode)
return 0;
}
+static int protection_domain_init_v2(struct protection_domain *domain)
+{
+ spin_lock_init(&domain->lock);
+ domain->id = domain_id_alloc();
+ if (!domain->id)
+ return -ENOMEM;
+ INIT_LIST_HEAD(&domain->dev_list);
+
+ domain->flags |= PD_GIOV_MASK;
+
+ if (domain_enable_v2(domain, 1)) {
+ domain_id_free(domain->id);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
static struct protection_domain *protection_domain_alloc(unsigned int type)
{
struct io_pgtable_ops *pgtbl_ops;
@@ -2048,6 +2070,9 @@ static struct protection_domain *protection_domain_alloc(unsigned int type)
case AMD_IOMMU_V1:
ret = protection_domain_init_v1(domain, mode);
break;
+ case AMD_IOMMU_V2:
+ ret = protection_domain_init_v2(domain);
+ break;
default:
ret = -EINVAL;
}
--
2.31.1
next prev parent reply other threads:[~2022-07-13 5:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 5:30 [PATCH v2 0/6] iommu/amd: Add Generic IO Page Table Framework Support for v2 Page Table Vasant Hegde
2022-07-13 5:30 ` [PATCH v2 1/6] iommu/amd: Refactor amd_iommu_domain_enable_v2 to remove locking Vasant Hegde
2022-07-13 5:30 ` [PATCH v2 2/6] iommu/amd: Update sanity check when enable PRI/ATS for IOMMU v1 table Vasant Hegde
2022-07-13 5:30 ` [PATCH v2 3/6] iommu/amd: Initial support for AMD IOMMU v2 page table Vasant Hegde
2022-07-15 11:55 ` Robin Murphy
2022-07-21 10:52 ` Vasant Hegde
2022-07-13 5:30 ` [PATCH v2 4/6] iommu/amd: Add support for Guest IO protection Vasant Hegde
2022-07-13 5:30 ` Vasant Hegde [this message]
2022-07-13 5:30 ` [PATCH v2 6/6] iommu/amd: Add command-line option to enable different page table Vasant Hegde
2022-07-15 8:49 ` [PATCH v2 0/6] iommu/amd: Add Generic IO Page Table Framework Support for v2 Page Table Joerg Roedel
2022-07-21 10:48 ` Vasant Hegde
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