From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FD421FDC for ; Fri, 29 Jul 2022 06:37:28 +0000 (UTC) X-UUID: 7b7eec386f014580a2acd9fe9cc588e4-20220729 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:cdc64c02-2135-4cd9-8515-3e780fa8acfb,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:51,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:51 X-CID-META: VersionHash:0f94e32,CLOUDID:ecf1b224-a982-4824-82d2-9da3b6056c2a,C OID:IGNORED,Recheck:0,SF:801,TC:nil,Content:3,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 7b7eec386f014580a2acd9fe9cc588e4-20220729 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 404504241; Fri, 29 Jul 2022 14:32:15 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 29 Jul 2022 14:32:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 29 Jul 2022 14:32:13 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , "Will Deacon" , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , "Matthias Brugger" , Tinghan Shen , AngeloGioacchino Del Regno , "MandyJH Liu" CC: , , , , , , Fengquan Chen Subject: [PATCH v4 08/20] arm64: dts: mt8195: Disable watchdog external reset signal Date: Fri, 29 Jul 2022 14:31:56 +0800 Message-ID: <20220729063208.16799-9-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220729063208.16799-1-tinghan.shen@mediatek.com> References: <20220729063208.16799-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Disable the external output reset signal of watchdog reset to avoid losing the reset reason stored in the watchdog registers. Signed-off-by: Fengquan Chen Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 066c14989708a..436687ba826f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -327,6 +327,7 @@ watchdog: watchdog@10007000 { compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; + mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; }; -- 2.18.0