From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A3D033E8 for ; Fri, 26 Aug 2022 12:18:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661516297; x=1693052297; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YmFC8zLHQfeuODp8Z0sRULA2gpiKXokbwxdTZ3Q4dXs=; b=UAs7ERSLCKKljx5pF+Rb0kqF0DXW1gnW+muk+vNJ6tTsbBkxCpyfmx5b RYY3nlEX/TVrG+/l+qVNmzlC6GoaySj3fQyRPnIQIWXAnaZRZDTaWMdaS c9cMbrkURuGaR4AzRKpOjQ4LSurgdPG5TzXmMN/sMia1DyyEvtWX7XeM4 gYbxAlNTQ1XlYkLMiiqOBYpEa4NeYdfQp7OI1Hokd3HpWnDKAojQVunx7 6HFwANz6+Z6w3mv2Ydpw9XuDaBZx1IbHIwv5sjWjgbpeYzwxE7gOhDb5a o6lnXxBvUmvbgiKWZ4l2TFIKOivMhzAR8H1YaW+sX9Be+vRJSdbxZyApq w==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="295765304" X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="295765304" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2022 05:18:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="606747749" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga007.jf.intel.com with ESMTP; 26 Aug 2022 05:18:08 -0700 From: Lu Baolu To: Joerg Roedel , Jason Gunthorpe , Christoph Hellwig , Bjorn Helgaas , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker , Dave Jiang , Fenghua Yu , Vinod Koul Cc: Eric Auger , Liu Yi L , Jacob jun Pan , Zhangfei Gao , Zhu Tony , iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v12 11/17] arm-smmu-v3: Add blocking domain support Date: Fri, 26 Aug 2022 20:11:35 +0800 Message-Id: <20220826121141.50743-12-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220826121141.50743-1-baolu.lu@linux.intel.com> References: <20220826121141.50743-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ARM SMMUv3 hardwares support blocking DMA transactions by clearing the translation table entries. This implements a real blocking domain to avoid using an empty UNMANAGED domain. Signed-off-by: Lu Baolu Tested-by: Zhangfei Gao --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f88541be8213..5520a9607758 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -88,6 +88,8 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { { 0, NULL}, }; +static void arm_smmu_detach_dev(struct arm_smmu_master *master); + static void parse_driver_options(struct arm_smmu_device *smmu) { int i = 0; @@ -2004,10 +2006,28 @@ static bool arm_smmu_capable(enum iommu_cap cap) } } +static int blocking_domain_attach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + + arm_smmu_detach_dev(master); + return 0; +} + +static struct iommu_domain blocking_domain = { + .ops = &(const struct iommu_domain_ops) { + .attach_dev = blocking_domain_attach_dev + } +}; + static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) { struct arm_smmu_domain *smmu_domain; + if (type == IOMMU_DOMAIN_BLOCKED) + return &blocking_domain; + if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_DMA_FQ && -- 2.25.1