From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51AFC1C27 for ; Wed, 21 Sep 2022 07:03:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663743823; x=1695279823; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=VLf2RXUYKKOmZoPjWdX8Te/gPeu4nHe4ezJN9Uc4fRI=; b=lZGj81ZvhRqwsi+TFPR/eo5IW6Ns24KLvlI0VkmysQrs9KIpN6JKXnDS v83KYUbeL5Sl50GFIUvlamfC5KKU5jA2jf+AgnWfwD+PaTe1/vJVqjryj SNHOP37eNVESsitg1apKGL5KdTNsXKVjNybvNr7Oj9U+aoEUlpcWBj6T3 YfYVm4Ku55BtDHUjNW7Yp5TSxT6EW4q4c9CJ44J3OyWOEO92yma2Apx8b SfMQhnnWHZymSjFBRk9k2y3TtbaH1u5J2fuqVdoiGHJjJntz9UHeh/PjO y1hbmvLpMxJirEFGAFF8z0BLVBXIpGlyTBVminKJlsT18oNEy5hvnRkmy w==; X-IronPort-AV: E=McAfee;i="6500,9779,10476"; a="363895854" X-IronPort-AV: E=Sophos;i="5.93,332,1654585200"; d="scan'208";a="363895854" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 00:03:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,332,1654585200"; d="scan'208";a="681648663" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 21 Sep 2022 00:03:38 -0700 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jacob Pan , linux-kernel@vger.kernel.org, Lu Baolu , Jerry Snitselaar Subject: [PATCH v2 1/1] iommu/vt-d: Avoid unnecessary global IRTE cache invalidation Date: Wed, 21 Sep 2022 14:57:41 +0800 Message-Id: <20220921065741.3572495-1-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some VT-d hardware implementations invalidate all interrupt remapping hardware translation caches as part of SIRTP flow. The VT-d spec adds a ESIRTPS (Enhanced Set Interrupt Remap Table Pointer Support, section 11.4.2 in VT-d spec) capability bit to indicate this. The spec also states in 11.4.4 that hardware also performs global invalidation on all interrupt remapping caches as part of Interrupt Remapping Disable operation if ESIRTPS capability bit is set. This checks the ESIRTPS capability bit and skip software global cache invalidation if it's set. Signed-off-by: Jacob Pan Signed-off-by: Lu Baolu Reviewed-by: Jerry Snitselaar --- drivers/iommu/intel/iommu.h | 1 + drivers/iommu/intel/irq_remapping.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) Change log: v2: - Add ESIRTPS check in iommu_disable_irq_remapping() path as well. v1: https://lore.kernel.org/r/20220919062523.3438951-2-baolu.lu@linux.intel.com diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 99cc75ecac63..bddf6c69587d 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -146,6 +146,7 @@ /* * Decoding Capability Register */ +#define cap_esirtps(c) (((c) >> 62) & 1) #define cap_fl5lp_support(c) (((c) >> 60) & 1) #define cap_pi_support(c) (((c) >> 59) & 1) #define cap_fl1gp_support(c) (((c) >> 56) & 1) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 2e9683e970f8..5962bb5027d0 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -494,7 +494,8 @@ static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) * Global invalidation of interrupt entry cache to make sure the * hardware uses the new irq remapping table. */ - qi_global_iec(iommu); + if (!cap_esirtps(iommu->cap)) + qi_global_iec(iommu); } static void iommu_enable_irq_remapping(struct intel_iommu *iommu) @@ -680,7 +681,8 @@ static void iommu_disable_irq_remapping(struct intel_iommu *iommu) * global invalidation of interrupt entry cache before disabling * interrupt-remapping. */ - qi_global_iec(iommu); + if (!cap_esirtps(iommu->cap)) + qi_global_iec(iommu); raw_spin_lock_irqsave(&iommu->register_lock, flags); -- 2.34.1