From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B3DBBA25 for ; Sun, 6 Nov 2022 22:02:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86607C433C1; Sun, 6 Nov 2022 22:02:10 +0000 (UTC) From: Catalin Marinas To: Linus Torvalds , Arnd Bergmann , Christoph Hellwig , Greg Kroah-Hartman Cc: Will Deacon , Marc Zyngier , Andrew Morton , Herbert Xu , Ard Biesheuvel , Isaac Manjarres , Saravana Kannan , Alasdair Kergon , Daniel Vetter , Joerg Roedel , Mark Brown , Mike Snitzer , "Rafael J. Wysocki" , Robin Murphy , linux-mm@kvack.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 06/13] dma: Allow the smaller cache_line_size() returned by dma_get_cache_alignment() Date: Sun, 6 Nov 2022 22:01:36 +0000 Message-Id: <20221106220143.2129263-7-catalin.marinas@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106220143.2129263-1-catalin.marinas@arm.com> References: <20221106220143.2129263-1-catalin.marinas@arm.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On architectures like arm64, ARCH_DMA_MINALIGN is larger than the majority of cache line size configurations. Allow an architecture to opt in to dma_get_cache_alignment() returning such smaller size and select the option for arm64. Signed-off-by: Catalin Marinas Cc: Christoph Hellwig Cc: Robin Murphy Cc: Will Deacon --- Is there any architecture where ARCH_DMA_MINALIGN is larger than cache_line_size()? We could avoid another Kconfig entry. arch/arm64/Kconfig | 1 + include/linux/dma-mapping.h | 2 ++ kernel/dma/Kconfig | 6 ++++++ 3 files changed, 9 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 505c8a1ccbe0..3991cb7b8a33 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -22,6 +22,7 @@ config ARM64 select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEBUG_VM_PGTABLE + select ARCH_HAS_DMA_CACHE_LINE_SIZE select ARCH_HAS_DMA_PREP_COHERENT select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI select ARCH_HAS_FAST_MULTIPLIER diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 3288a1339271..b29124341317 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -545,6 +545,8 @@ static inline int dma_set_min_align_mask(struct device *dev, static inline int dma_get_cache_alignment(void) { + if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CACHE_LINE_SIZE)) + return cache_line_size(); #ifdef ARCH_HAS_DMA_MINALIGN return ARCH_DMA_MINALIGN; #endif diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 56866aaa2ae1..d6fab8e3cbae 100644 --- a/kernel/dma/Kconfig +++ b/kernel/dma/Kconfig @@ -76,6 +76,12 @@ config ARCH_HAS_DMA_PREP_COHERENT config ARCH_HAS_FORCE_DMA_UNENCRYPTED bool +config ARCH_HAS_DMA_CACHE_LINE_SIZE + bool + help + Select if the architecture has non-coherent DMA and + cache_line_size() is a safe alignment for DMA buffers. + config SWIOTLB bool select NEED_DMA_MAP_STATE