From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E06F77F for ; Fri, 7 Jul 2023 01:34:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688693698; x=1720229698; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=JAYSCFUQt9c5CCD8SI1JBKYefNqsH+DVavhBCVsUaR4=; b=PcI+FqQelUdgIBWEsmFhaOagisQIdlJFKLMgb41KvcR2TPepqNYw38qi BKHVDtS7qC+eCMBaZShKJrNVmSlR1qtk8bV+QlRayJUbhG1nrgX5VTV5X V2uYEuclv5DRIobNwIPyqSjmOo99RZAC86348FkJm8RUGFL7Sb6+4LifT p1TI9x0Ha6UFVZ4XHRBryL+nPUYKs61eU5FpLXTgpT+MV88+qmlMGIlPd eYsnB8fPzwvyRjk4Ee8z2PvwfcJeBvtr8J96ExbbmC38ZxOiD9UvTnHsp o5fIa93rAtpGfsQhQ8AauaP8bXKtGoSDEUIQEgki/ibGkGepG2NtQI40l Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10763"; a="429832233" X-IronPort-AV: E=Sophos;i="6.01,187,1684825200"; d="scan'208";a="429832233" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2023 18:34:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10763"; a="893791280" X-IronPort-AV: E=Sophos;i="6.01,187,1684825200"; d="scan'208";a="893791280" Received: from fengj-mobl.ccr.corp.intel.com (HELO tinazhan-desk1.www.tendawifi.com) ([10.254.210.124]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2023 18:34:55 -0700 From: Tina Zhang To: Jason Gunthorpe , Kevin Tian , Joerg Roedel , Will Deacon , Lu Baolu , Michael Shavit Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Tina Zhang Subject: [RFC PATCH 0/6] Share sva domain with all devices bound to a mm Date: Fri, 7 Jul 2023 09:34:35 +0800 Message-Id: <20230707013441.365583-1-tina.zhang@intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit During a sva domain's life time, which begins with binding a device to a mm and ends by releasing all the bound devices from that mm, there is only one PASID assigned for this sva domain. From platform perspective, supporting 1:1 mapping between mm PASID and sva domain allows a sva domain to be shared by mm's all bound devices issuing DMA transactions using the assigned PASID. To support mm PASID 1:1 with sva domain, each mm needs to keep both a reference of an allocated sva domain and its corresponding PASID. However, currently, mm struct only has one pasid field for sva usage, which is used to keep the info of an assigned PASID. That pasid field cannot provide sufficient info to build up the 1:1 mapping between sva domain and PASID. This patch-set fills the gap by adding an mm_iommu field[1], whose type is mm_iommu_data struct, to replace the old pasid field. The introduced mm_iommu_data struct keeps info of both a sva domain reference and an assigned PASID. [1]: https://lore.kernel.org/linux-iommu/ZIBxPd1%2FJCAle6yP@nvidia.com/ Tina Zhang (6): iommu: Add two pasid helper functions iommu: Call helper functions to get/set assigned pasid value iommu: Introduce struct iommu_mm_data mm: Add iommu_mm field to mm_struct iommu: Support mm PASID 1:1 with sva domain mm: Deprecate pasid field arch/x86/kernel/traps.c | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 12 ++-- drivers/iommu/intel/svm.c | 8 +-- drivers/iommu/iommu-sva.c | 68 ++++++++++++------- drivers/iommu/iommu.c | 3 + include/linux/iommu.h | 25 ++++++- include/linux/mm_types.h | 2 + mm/init-mm.c | 2 +- 8 files changed, 84 insertions(+), 38 deletions(-) -- 2.34.1