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Fri, 28 Jul 2023 00:39:58 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v2 12/16] iommu/amd: Add support for different types of PPR handler Date: Fri, 28 Jul 2023 05:36:05 +0000 Message-ID: <20230728053609.165183-13-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230728053609.165183-1-vasant.hegde@amd.com> References: <20230728053609.165183-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT030:EE_|DS7PR12MB8291:EE_ X-MS-Office365-Filtering-Correlation-Id: 26904897-b2cd-44bb-9cd1-08db8f2d167b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2023 05:40:01.6088 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26904897-b2cd-44bb-9cd1-08db8f2d167b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8291 From: Suravee Suthikulpanit For AMD IOMMU, the PPR feature is needed to support IO page fault (IOPF). PPR is enabled per PCI end-point device, and is configured by the PPR bit in the IOMMU device table entry (i.e DTE[PPR]). Currently, PPR is enabled for a device when it is initialized for AMD IOMMU v2API. To support paging for IOPF, the DTE[PPR] bit needs to be updated when enable/disable IOPF feature. Introducing struct iommu_dev_data.ppr and enum ppr_handlers to track PPR setting for each device. Finally iommu_dev_data.ppr is set only when IOMMU supports PPR. Hence remove redundant feature support check in set_dte_entry(). Signed-off-by: Suravee Suthikulpanit Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu_types.h | 7 +++++++ drivers/iommu/amd/iommu.c | 10 ++++------ drivers/iommu/amd/iommu_v2.c | 14 +++++++++++++- 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index a066f375ba87..321d361dfb60 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -803,6 +803,12 @@ struct devid_map { bool cmd_line; }; +enum ppr_handlers { + PPR_HANDLER_NONE, /* No handler specified */ + PPR_HANDLER_V2API, /* IOMMU v2 API ppr handler */ + PPR_HANDLER_IOPF, /* IOPF ppr handler */ +}; + /* * This struct contains device specific data for the IOMMU */ @@ -820,6 +826,7 @@ struct iommu_dev_data { bool ats_enabled; /* ATS state */ bool pri_tlp; /* PASID TLB required for PPR completions */ + enum ppr_handlers ppr; bool use_vapic; /* Enable device to use vapic mode */ bool defer_attach; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 5a4170592bf4..e67c6fae452c 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1631,10 +1631,8 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid, if (ats) flags |= DTE_FLAG_IOTLB; - if (ppr) { - if (iommu_feature(iommu, FEATURE_EPHSUP)) - pte_root |= 1ULL << DEV_ENTRY_PPR; - } + if (ppr) + pte_root |= 1ULL << DEV_ENTRY_PPR; if (domain->flags & PD_IOMMUV2_MASK) { u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); @@ -1727,7 +1725,7 @@ static void do_attach(struct iommu_dev_data *dev_data, /* Update device table */ set_dte_entry(iommu, dev_data->devid, domain, - ats, dev_data->iommu_v2); + ats, dev_data->ppr); clone_aliases(iommu, dev_data->dev); device_flush_dte(dev_data); @@ -2006,7 +2004,7 @@ static void update_device_table(struct protection_domain *domain) if (!iommu) continue; set_dte_entry(iommu, dev_data->devid, domain, - dev_data->ats_enabled, dev_data->iommu_v2); + dev_data->ats_enabled, dev_data->ppr); clone_aliases(iommu, dev_data->dev); } } diff --git a/drivers/iommu/amd/iommu_v2.c b/drivers/iommu/amd/iommu_v2.c index 9bf114382c00..4148cbf069dc 100644 --- a/drivers/iommu/amd/iommu_v2.c +++ b/drivers/iommu/amd/iommu_v2.c @@ -740,6 +740,10 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids) unsigned long flags; int ret, tmp; u32 sbdf; + struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev); + + if (!dev_data) + return -ENODEV; might_sleep(); @@ -762,6 +766,9 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids) if (dev_state == NULL) return -ENOMEM; + /* Enable device for PPR support */ + dev_data->ppr = PPR_HANDLER_V2API; + spin_lock_init(&dev_state->lock); init_waitqueue_head(&dev_state->wq); dev_state->pdev = pdev; @@ -832,6 +839,8 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids) out_free_dev_state: kfree(dev_state); + dev_data->ppr = PPR_HANDLER_NONE; + return ret; } EXPORT_SYMBOL(amd_iommu_init_device); @@ -841,8 +850,9 @@ void amd_iommu_free_device(struct pci_dev *pdev) struct device_state *dev_state; unsigned long flags; u32 sbdf; + struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev); - if (!amd_iommu_v2_supported()) + if (!dev_data || !amd_iommu_v2_supported()) return; sbdf = get_pci_sbdf_id(pdev); @@ -859,6 +869,8 @@ void amd_iommu_free_device(struct pci_dev *pdev) spin_unlock_irqrestore(&state_lock, flags); + dev_data->ppr = PPR_HANDLER_NONE; + put_device_state(dev_state); free_device_state(dev_state); } -- 2.31.1