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Wed, 16 Aug 2023 12:43:14 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v2 09/10] iommu/amd: Refactor GCR3 table helper functions Date: Wed, 16 Aug 2023 17:40:30 +0000 Message-ID: <20230816174031.634453-10-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230816174031.634453-1-vasant.hegde@amd.com> References: <20230816174031.634453-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|CY5PR12MB6083:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f65a5d3-f42e-4529-7784-08db9e804665 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5Zm7iEczlNnQKWrHbtIKcj5K1UnaPSWK36qhsvtWuMbUxBveMro1zV1i1t0OPXlA9UDME44fDBofSQd3+WETu1IqohIyt8U4tRg0YYF5XUecGnz8cFl2p80TX9ySBJXuMOZ/HtlAZgEDGbDp32JOSuaBVOU8A2dv7ku8Iar0wbGBzzScsbAFG+f4nAdTxPP82slW+2vyJ0Z01rL25bTRZkchERLMilWFZ3ode8gzKZi+/5H63Uz5ZB1ghBNSw8JJB2T3ddRUjW+7jaxfs56CIGBdQRcR6y8yYbAzdDH8r53OPWfm4uxQo1IVFt4qGrvdKB5u2lLxiSFQsUqznS5OpHDHcjnC4shl6SpZwAZpfzWRzdC7/VzVvRqQcaMhk3gasxTft8Wt9bQdlQ/KJAh4XeIsCm64Zqu+zsxJfMvBBZrFvX6pLZo5cqssAied+4DVBTmRLA62fqOcr48+QtZQqvMMFqOqYRzk9ZoKOK4E9hsGQ4NWpkCZnv8tigWy+rooSj0nSixpSYc14ZVTTqqmEBO0OZ7nE3fk6ttA84UbvSeOFqUifD4h8NvKxIeaT8mCsNB6lflWeJyzqA1+Syc2nNwcmGznftCIGhIxC/pPlNCbC8QmzeBACnTzdueKox/rs4XnTmSVQgmJh3glttXAO6BG2w8rJjp2Rs6h54Y5heEIQCfnjPfMf4mKsJdBHVqk/XM1cFSbMX0LmfsUE1SN6JAn1ZJTo1WfX1IKuBe08ReE0iPHIiwHBr8cPFGERGsvR//j3htS7PhQWE6q8LsxvQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199024)(1800799009)(82310400011)(186009)(46966006)(36840700001)(40470700004)(2906002)(40460700003)(83380400001)(86362001)(40480700001)(478600001)(426003)(336012)(36756003)(7696005)(2616005)(6666004)(1076003)(26005)(16526019)(5660300002)(44832011)(36860700001)(41300700001)(356005)(54906003)(82740400003)(316002)(81166007)(70206006)(70586007)(110136005)(8676002)(8936002)(4326008)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 17:43:17.5395 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f65a5d3-f42e-4529-7784-08db9e804665 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6083 From: Suravee Suthikulpanit To use the new per-device struct gcr3_tbl_info. Also modify set_dte_entry() to use new per device GCR3 table. Signed-off-by: Suravee Suthikulpanit Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde --- drivers/iommu/amd/iommu.c | 76 ++++++++++++++++++++++++++------------- 1 file changed, 51 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index be68d77861f5..8d3d520a525a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -77,6 +77,11 @@ struct kmem_cache *amd_iommu_irq_cache; static void detach_device(struct device *dev); +static void set_dte_entry(struct amd_iommu *iommu, u16 devid, + struct gcr3_tbl_info *gcr3_info, + struct protection_domain *domain, bool ats, + bool ppr); + static int __set_gcr3(struct iommu_dev_data *dev_data, u32 pasid, unsigned long gcr3); @@ -1659,16 +1664,27 @@ static void free_gcr3_tbl_level2(u64 *tbl) } } -static void free_gcr3_table(struct protection_domain *domain) +static void free_gcr3_table(struct iommu_dev_data *dev_data) { - if (domain->glx == 2) - free_gcr3_tbl_level2(domain->gcr3_tbl); - else if (domain->glx == 1) - free_gcr3_tbl_level1(domain->gcr3_tbl); + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); + + if (gcr3_info->glx == 2) + free_gcr3_tbl_level2(gcr3_info->gcr3_tbl); + else if (gcr3_info->glx == 1) + free_gcr3_tbl_level1(gcr3_info->gcr3_tbl); else - BUG_ON(domain->glx != 0); + WARN_ON_ONCE(gcr3_info->glx != 0); - free_page((unsigned long)domain->gcr3_tbl); + gcr3_info->glx = 0; + + set_dte_entry(iommu, dev_data->devid, NULL, dev_data->domain, + dev_data->ats_enabled, dev_data->ppr); + clone_aliases(iommu, dev_data->dev); + device_flush_dte(dev_data); + + free_page((unsigned long)gcr3_info->gcr3_tbl); + gcr3_info->gcr3_tbl = NULL; } /* @@ -1687,28 +1703,37 @@ static int get_gcr3_levels(int pasids) return levels ? (DIV_ROUND_UP(levels, 9) - 1) : levels; } -/* Note: This function expects iommu_domain->lock to be held prior calling the function. */ -static int setup_gcr3_table(struct protection_domain *domain, int pasids) +static int setup_gcr3_table(struct iommu_dev_data *dev_data, int pasids) { + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); int levels = get_gcr3_levels(pasids); if (levels > amd_iommu_max_glx_val) return -EINVAL; - domain->gcr3_tbl = alloc_pgtable_page(domain->nid, GFP_ATOMIC); - if (domain->gcr3_tbl == NULL) + if (gcr3_info->gcr3_tbl) + return -EBUSY; + + gcr3_info->gcr3_tbl = alloc_pgtable_page(dev_to_node(dev_data->dev), + GFP_ATOMIC); + if (gcr3_info->gcr3_tbl == NULL) return -ENOMEM; - domain->glx = levels; - domain->flags |= PD_IOMMUV2_MASK; + gcr3_info->glx = levels; - amd_iommu_domain_update(domain); + set_dte_entry(iommu, dev_data->devid, &dev_data->gcr3_info, + dev_data->domain, dev_data->ats_enabled, dev_data->ppr); + clone_aliases(iommu, dev_data->dev); + device_flush_dte(dev_data); return 0; } static void set_dte_entry(struct amd_iommu *iommu, u16 devid, - struct protection_domain *domain, bool ats, bool ppr) + struct gcr3_tbl_info *gcr3_info, + struct protection_domain *domain, bool ats, + bool ppr) { u64 pte_root = 0; u64 flags = 0; @@ -1738,9 +1763,9 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid, if (ppr) pte_root |= 1ULL << DEV_ENTRY_PPR; - if (domain->flags & PD_IOMMUV2_MASK) { - u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); - u64 glx = domain->glx; + if (gcr3_info && gcr3_info->gcr3_tbl) { + u64 gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl); + u64 glx = gcr3_info->glx; u64 tmp; pte_root |= DTE_FLAG_GV; @@ -1768,7 +1793,7 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid, ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); } - if (domain->flags & PD_GIOV_MASK) + if (gcr3_info->giov) pte_root |= DTE_FLAG_GIOV; } @@ -1815,7 +1840,7 @@ static int _init_gcr3_tbl(struct iommu_dev_data *dev_data) * By default, setup GCR3 table to support MAX PASIDs * support by the IOMMU HW. */ - return setup_gcr3_table(dev_data->domain, -1); + return setup_gcr3_table(dev_data, -1); } static inline void _destroy_gcr3_tbl(struct iommu_dev_data *dev_data) @@ -1823,7 +1848,7 @@ static inline void _destroy_gcr3_tbl(struct iommu_dev_data *dev_data) struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; gcr3_info->giov = false; - free_gcr3_table(dev_data->domain); + free_gcr3_table(dev_data); } static int do_attach(struct iommu_dev_data *dev_data, @@ -1864,8 +1889,8 @@ static int do_attach(struct iommu_dev_data *dev_data, } /* Update device table */ - set_dte_entry(iommu, dev_data->devid, domain, - ats, dev_data->ppr); + set_dte_entry(iommu, dev_data->devid, &dev_data->gcr3_info, + domain, ats, dev_data->ppr); clone_aliases(iommu, dev_data->dev); device_flush_dte(dev_data); @@ -2068,8 +2093,9 @@ static void update_device_table(struct protection_domain *domain) if (!iommu) continue; - set_dte_entry(iommu, dev_data->devid, domain, - dev_data->ats_enabled, dev_data->ppr); + + set_dte_entry(iommu, dev_data->devid, &dev_data->gcr3_info, + domain, dev_data->ats_enabled, dev_data->ppr); clone_aliases(iommu, dev_data->dev); } } -- 2.31.1