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Wed, 16 Aug 2023 12:41:06 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v2 01/10] iommu/amd: Use struct protection_domain in helper functions Date: Wed, 16 Aug 2023 17:40:22 +0000 Message-ID: <20230816174031.634453-2-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230816174031.634453-1-vasant.hegde@amd.com> References: <20230816174031.634453-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|DS7PR12MB5813:EE_ X-MS-Office365-Filtering-Correlation-Id: 1146eadc-3f89-40e0-6e24-08db9e7ff995 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 17:41:08.7787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1146eadc-3f89-40e0-6e24-08db9e7ff995 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5813 From: Suravee Suthikulpanit To simplify the unnecessary use of container_of() on the struct iommu_domain to get the container structure. No functional changes intended. Signed-off-by: Suravee Suthikulpanit Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu.h | 13 +++++++++---- drivers/iommu/amd/io_pgtable_v2.c | 8 ++++---- drivers/iommu/amd/iommu.c | 18 ++++-------------- 3 files changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 8b586effbefc..87739d95ea8b 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -55,15 +55,15 @@ int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev); void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev); -int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address); +int amd_iommu_flush_page(struct protection_domain *domain, u32 pasid, u64 address); void amd_iommu_update_and_flush_device_table(struct protection_domain *domain); void amd_iommu_domain_update(struct protection_domain *domain); void amd_iommu_domain_flush_complete(struct protection_domain *domain); void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain); -int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid); -int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, +int amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid); +int amd_iommu_domain_set_gcr3(struct protection_domain *domain, u32 pasid, unsigned long cr3); -int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid); +int amd_iommu_domain_clear_gcr3(struct protection_domain *domain, u32 pasid); #ifdef CONFIG_IRQ_REMAP int amd_iommu_create_irq_domain(struct amd_iommu *iommu); @@ -147,6 +147,11 @@ static inline void *alloc_pgtable_page(int nid, gfp_t gfp) return page ? page_address(page) : NULL; } +static inline struct protection_domain *to_pdomain(struct iommu_domain *dom) +{ + return container_of(dom, struct protection_domain, domain); +} + bool translation_pre_enabled(struct amd_iommu *iommu); bool amd_iommu_is_attach_deferred(struct device *dev); int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line); diff --git a/drivers/iommu/amd/io_pgtable_v2.c b/drivers/iommu/amd/io_pgtable_v2.c index f818a7e254d4..c17cda83bca5 100644 --- a/drivers/iommu/amd/io_pgtable_v2.c +++ b/drivers/iommu/amd/io_pgtable_v2.c @@ -274,9 +274,9 @@ static int iommu_v2_map_pages(struct io_pgtable_ops *ops, unsigned long iova, out: if (updated) { if (count > 1) - amd_iommu_flush_tlb(&pdom->domain, 0); + amd_iommu_flush_tlb(pdom, 0); else - amd_iommu_flush_page(&pdom->domain, 0, o_iova); + amd_iommu_flush_page(pdom, 0, o_iova); } if (mapped) @@ -364,7 +364,7 @@ static void v2_free_pgtable(struct io_pgtable *iop) return; /* Clear gcr3 entry */ - amd_iommu_domain_clear_gcr3(&pdom->domain, 0); + amd_iommu_domain_clear_gcr3(pdom, 0); /* Make changes visible to IOMMUs */ amd_iommu_domain_update(pdom); @@ -384,7 +384,7 @@ static struct io_pgtable *v2_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo if (!pgtable->pgd) return NULL; - ret = amd_iommu_domain_set_gcr3(&pdom->domain, 0, iommu_virt_to_phys(pgtable->pgd)); + ret = amd_iommu_domain_set_gcr3(pdom, 0, iommu_virt_to_phys(pgtable->pgd)); if (ret) goto err_free_pgd; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 8e4f52d8bc9d..fca6e6ceeef3 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -173,11 +173,6 @@ static struct amd_iommu *rlookup_amd_iommu(struct device *dev) return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid)); } -static struct protection_domain *to_pdomain(struct iommu_domain *dom) -{ - return container_of(dom, struct protection_domain, domain); -} - static struct iommu_dev_data *alloc_dev_data(struct amd_iommu *iommu, u16 devid) { struct iommu_dev_data *dev_data; @@ -2592,10 +2587,8 @@ static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid, return __flush_pasid(domain, pasid, address, false); } -int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, - u64 address) +int amd_iommu_flush_page(struct protection_domain *domain, u32 pasid, u64 address) { - struct protection_domain *domain = to_pdomain(dom); unsigned long flags; int ret; @@ -2612,9 +2605,8 @@ static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid) true); } -int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid) +int amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid) { - struct protection_domain *domain = to_pdomain(dom); unsigned long flags; int ret; @@ -2690,10 +2682,9 @@ static int __clear_gcr3(struct protection_domain *domain, u32 pasid) return __amd_iommu_flush_tlb(domain, pasid); } -int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, +int amd_iommu_domain_set_gcr3(struct protection_domain *domain, u32 pasid, unsigned long cr3) { - struct protection_domain *domain = to_pdomain(dom); unsigned long flags; int ret; @@ -2704,9 +2695,8 @@ int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, return ret; } -int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid) +int amd_iommu_domain_clear_gcr3(struct protection_domain *domain, u32 pasid) { - struct protection_domain *domain = to_pdomain(dom); unsigned long flags; int ret; -- 2.31.1