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Wed, 23 Aug 2023 09:05:51 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH RESEND 04/10] iommu/amd: Add support to enable/disable SVA feature Date: Wed, 23 Aug 2023 14:04:09 +0000 Message-ID: <20230823140415.729050-5-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230823140415.729050-1-vasant.hegde@amd.com> References: <20230823140415.729050-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A8:EE_|BL1PR12MB5947:EE_ X-MS-Office365-Filtering-Correlation-Id: 393030d4-089e-4030-5f2f-08dba3e21151 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2023 14:05:55.0132 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 393030d4-089e-4030-5f2f-08dba3e21151 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5947 From: Suravee Suthikulpanit Add support to enable/disable SVA feature. It will setup v2 page table mode with PASID and enables SVA. Signed-off-by: Suravee Suthikulpanit Co-developed-by: Wei Huang Signed-off-by: Wei Huang Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu.h | 4 +++ drivers/iommu/amd/iommu.c | 63 +++++++++++++++++++++++++++++++++++ drivers/iommu/amd/sva.c | 29 ++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 6fdad7a54781..3f7ddf19ed72 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -46,6 +46,10 @@ bool amd_iommu_sva_supported(void); int amd_iommu_set_dev_pasid(struct iommu_domain *domain, struct device *dev, ioasid_t pasid); void amd_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid); +int amd_iommu_sva_enable(struct device *dev); +int amd_iommu_sva_disable(struct device *dev); +int amd_iommu_sva_gcr3_init(struct iommu_dev_data *dev_data, int pasids); +int amd_iommu_sva_gcr3_uninit(struct iommu_dev_data *dev_data); struct amd_iommu *get_amd_iommu(unsigned int idx); u8 amd_iommu_pc_get_max_banks(unsigned int idx); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 46bb1bfdc322..4868eee4c4f9 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2162,6 +2162,63 @@ static void protection_domain_free(struct protection_domain *domain) kfree(domain); } +/******************************* + * SVA-related helper functions + */ +static inline bool pdom_is_pt_mode(struct protection_domain *pdom) +{ + return (pdom->domain.type == IOMMU_DOMAIN_IDENTITY); +} + +static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom) +{ + return (pdom->iop.pgd != NULL); +} + +int amd_iommu_sva_gcr3_init(struct iommu_dev_data *dev_data, int pasids) +{ + struct protection_domain *pdom = dev_data->domain; + unsigned long flags; + int ret = 0; + + /* + * We cannot support SVA w/ existing v1 page table in the same domain + * since it will be nested. However, existing domain w/ v2 pagetable + * can be used for SVA. + */ + if (pdom->pd_mode == PD_MODE_V1) + return -EOPNOTSUPP; + + spin_lock_irqsave(&dev_data->lock, flags); + + /* Allocate GCR3 table */ + if (pdom_is_pt_mode(dev_data->domain)) + ret = setup_gcr3_table(dev_data, pasids); + + spin_unlock_irqrestore(&dev_data->lock, flags); + return ret; +} + +int amd_iommu_sva_gcr3_uninit(struct iommu_dev_data *dev_data) +{ + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; + unsigned long flags; + + spin_lock_irqsave(&dev_data->lock, flags); + + if (gcr3_info->pasid_cnt) { + spin_unlock_irqrestore(&dev_data->lock, flags); + return -EBUSY; + } + + /* Free GCR3 table */ + if (pdom_is_pt_mode(dev_data->domain)) + free_gcr3_table(dev_data); + + spin_unlock_irqrestore(&dev_data->lock, flags); + return 0; +} + static int protection_domain_init_v1(struct protection_domain *domain, int mode) { u64 *pt_root = NULL; @@ -2578,6 +2635,9 @@ static int amd_iommu_dev_enable_feature(struct device *dev, int ret; switch (feat) { + case IOMMU_DEV_FEAT_SVA: + ret = amd_iommu_sva_enable(dev); + break; default: ret = -EINVAL; break; @@ -2591,6 +2651,9 @@ static int amd_iommu_dev_disable_feature(struct device *dev, int ret; switch (feat) { + case IOMMU_DEV_FEAT_SVA: + ret = amd_iommu_sva_disable(dev); + break; default: ret = -EINVAL; break; diff --git a/drivers/iommu/amd/sva.c b/drivers/iommu/amd/sva.c index c7c7e7cb5414..b4cc5b854753 100644 --- a/drivers/iommu/amd/sva.c +++ b/drivers/iommu/amd/sva.c @@ -297,3 +297,32 @@ void amd_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid) break; } } + +int amd_iommu_sva_enable(struct device *dev) +{ + struct pci_dev *pdev = dev_is_pci(dev) ? to_pci_dev(dev) : NULL; + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev); + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); + + if (!pdev || !iommu || !dev_data) + return -EINVAL; + + if (!amd_iommu_sva_supported()) + return -ENODEV; + + if (!dev_data->pasid_enabled) + return -EINVAL; + + return amd_iommu_sva_gcr3_init(dev_data, dev->iommu->max_pasids); +} + +int amd_iommu_sva_disable(struct device *dev) +{ + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev); + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); + + if (!iommu || !dev_data) + return -EINVAL; + + return amd_iommu_sva_gcr3_uninit(dev_data); +} -- 2.31.1