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Mon, 11 Sep 2023 07:14:45 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v2 11/11] iommu/amd: Introduce logic to enable/disable IOPF Date: Mon, 11 Sep 2023 12:10:46 +0000 Message-ID: <20230911121046.1025732-12-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230911121046.1025732-1-vasant.hegde@amd.com> References: <20230911121046.1025732-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|MN2PR12MB4077:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c3dc544-10c9-419e-1c33-08dbb2c0b169 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2023 12:14:48.2509 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c3dc544-10c9-419e-1c33-08dbb2c0b169 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4077 From: Suravee Suthikulpanit Add support to enable/disable IOPF feature. So that PRI capable device can make use of page fault handler in SVA mode. Also add IOMMU_IOPF as dependency to AMD_IOMMU driver. Signed-off-by: Suravee Suthikulpanit Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde --- drivers/iommu/amd/Kconfig | 1 + drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/iommu.c | 6 ++++ drivers/iommu/amd/ppr.c | 56 +++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+) diff --git a/drivers/iommu/amd/Kconfig b/drivers/iommu/amd/Kconfig index cabf4ccde1ed..22e33179c593 100644 --- a/drivers/iommu/amd/Kconfig +++ b/drivers/iommu/amd/Kconfig @@ -11,6 +11,7 @@ config AMD_IOMMU select IOMMU_IOVA select IOMMU_IO_PGTABLE select IOMMU_SVA + select IOMMU_IOPF depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE help With this option you can enable support for AMD IOMMU hardware in diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 14198cade320..7dbd9e54f48f 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -62,6 +62,8 @@ int amd_iommu_iopf_remove_device(struct amd_iommu *iommu, struct device *dev); int amd_iommu_page_response(struct device *dev, struct iopf_fault *evt, struct iommu_page_response *resp); +int amd_iommu_iopf_enable(struct device *dev); +int amd_iommu_iopf_disable(struct device *dev); struct amd_iommu *get_amd_iommu(unsigned int idx); u8 amd_iommu_pc_get_max_banks(unsigned int idx); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 35221deb848b..1be5fdab70d0 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2574,6 +2574,9 @@ static int amd_iommu_dev_enable_feature(struct device *dev, case IOMMU_DEV_FEAT_SVA: ret = 0; break; + case IOMMU_DEV_FEAT_IOPF: + ret = amd_iommu_iopf_enable(dev); + break; default: ret = -EINVAL; break; @@ -2590,6 +2593,9 @@ static int amd_iommu_dev_disable_feature(struct device *dev, case IOMMU_DEV_FEAT_SVA: ret = 0; break; + case IOMMU_DEV_FEAT_IOPF: + ret = amd_iommu_iopf_disable(dev); + break; default: ret = -EINVAL; break; diff --git a/drivers/iommu/amd/ppr.c b/drivers/iommu/amd/ppr.c index 2891f67a6ca0..86c0cb836a71 100644 --- a/drivers/iommu/amd/ppr.c +++ b/drivers/iommu/amd/ppr.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "amd_iommu.h" #include "amd_iommu_types.h" @@ -306,3 +307,58 @@ int amd_iommu_iopf_remove_device(struct amd_iommu *iommu, struct device *dev) raw_spin_unlock_irqrestore(&iommu->lock, flags); return ret; } + +static int amd_iommu_iopf_update(struct device *dev, bool enable) +{ + unsigned long flags; + int ret; + struct pci_dev *pdev = dev_is_pci(dev) ? to_pci_dev(dev) : NULL; + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev); + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); + struct protection_domain *pdom = amd_iommu_get_pdomain(dev); + + if (!pdev || !iommu || !dev_data) + return -EINVAL; + + spin_lock_irqsave(&pdom->lock, flags); + + if (enable) { + ret = amd_iommu_iopf_add_device(iommu, dev); + if (ret) + goto out; + + dev_data->ppr = true; + } else { + ret = amd_iommu_iopf_remove_device(iommu, dev); + dev_data->ppr = false; + } + + amd_iommu_domain_update(pdom); + +out: + spin_unlock_irqrestore(&pdom->lock, flags); + return ret; +} + +int amd_iommu_iopf_enable(struct device *dev) +{ + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); + + if (!(dev_data->flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP)) + return -ENODEV; + + if (!dev_data->ats_enabled || !dev_data->pri_enabled) + return -EINVAL; + + return amd_iommu_iopf_update(dev, true); +} + +int amd_iommu_iopf_disable(struct device *dev) +{ + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); + + if (!dev_data->pri_enabled) + return -EINVAL; + + return amd_iommu_iopf_update(dev, false); +} -- 2.31.1